Why Warpage Is the Key Challenge for AI Chip Packaging

A Deep Dive into Low-Temperature Curable PSPI, Balance Film, and the Supplier Landscape

The AI infrastructure buildout is often discussed in terms of chips and computing power. But beneath the surface, a set of supply chain bottlenecks is quietly shaping the pace and cost of deployment. Last week, we looked at glass substrates, and noted that warpage remains one of the major barriers to panel-level packaging at scale. This week, we go deeper: what’s actually causing the warp, and which materials are being developed to fix it.

Glass Substrates Are Breaking Through the AI Chip Packaging Bottleneck

As AI and HPC workloads drive chip packages to ever-larger form factors, the area utilization limits of circular wafers are becoming an increasingly important consideration. Panel-Level Packaging (PLP) addresses this directly by moving to square panels, which deliver higher area utilization and better alignment with large-die form factors.

Major foundries and OSATs including TSMC, Intel, Samsung, Rapidus, and Amkor are all advancing their PLP roadmaps. TSMC, through its subsidiary VisEra, plans to establish a CoPoS pilot line with trial production targeted for 2027, positioning 2026 as a critical window for product validation and deliveries for related equipment and material providers.

The central technical challenge, however, is warpage. As panel size grows and layer counts increase, thermal stress from CTE mismatches between materials compounds in ways that directly affect yield. To address this issue, specialty chemical suppliers such as AMC, WaferChem, and Everlight Chemical showcased corresponding solutions at Touch Taiwan 2026 in April. This article focuses on two key material approaches, Low-Temperature Curable PSPI and Balance Film, and maps out the current supplier landscape.

From Round to Square: The Rise of PLP

As AI model parameters grow exponentially, demand for computing performance continues to rise. With semiconductor process scaling approaching its physical limits, the industry has turned to assembling and stacking multiple chiplets on a single interposer to boost performance, driving a steady increase in package size. TSMC expects to achieve a 9.5x reticle size with its CoWoS-L packaging by 2027, while Intel plans to reach a 12x reticle size with its EMIB packaging by 2028.

Related report: Global AI Server & Supply Chain Outlook 2026

However, the continuous expansion of package sizes presents two major challenges: (1) the inefficiency of fitting square chips onto the edges of circular wafers, which reduces the area utilization rate for large-size packages; and (2) increasingly severe warpage issues, where warped sections of the substrate lead to poor contact.

To overcome these limitations, panel-level packaging (PLP) has come to the forefront. By transitioning from circular wafers to square or rectangular panels, chip edges can align seamlessly with the panel edges, thereby improving area utilization.

Currently, foundries, OSATs, material suppliers, and traditional LCD panel makers are all actively developing PLP technology. Mass production has been reached for relatively mature processes, such as the ones used to manufacture RF chips and PMICs (with an RDL L/S of approximately 10-20 μm). Conversely, advanced PLP processes for AI chips (with an RDL L/S of approximately 1-10 μm) have not yet entered mass production. Meanwhile, the industry is actively exploring both material and equipment solutions to address the warpage challenge.

What Causes Warpage and How to Fix It

The main cause of warpage is CTE mismatch between different materials, which generates stress differences during temperature changes and leads to bending. The magnitude of warpage is measured as the vertical distance between the highest and lowest points of the deformed surface, known as the peak-to-valley distance.

This problem increases non‑linearly with factors such as (1) larger panel area, (2) greater variety of materials, (3) larger CTE gaps between materials, (4) thinner thickness, and (5) more RDL layers. Whether the deformation appears as a concave ( “smiling face”) or convex (“frowning face”) profile, the result is poor contact between the chiplet and the panel.

Notably, the “chip-first” and “chip-last” processes in advanced packaging involve different warpage mechanisms, with variations in both timing and severity.

(1) Chip First：

The chip-first process comes in two variants: face-up and face-down. In the face-up approach, chips are mounted onto a glass carrier and encapsulated. The epoxy molding compound (EMC) is then ground down to expose the chip before the RDL is fabricated. In the face-down approach, the glass carrier is removed immediately after chip encapsulation, and the RDL is fabricated on the underside.

(2) Chip Last：

In the chip-last process, the RDL is fabricated on a glass carrier first, and the chip is mounted and encapsulated afterward. Because encapsulation occurs after RDL fabrication, the accumulated thermal stress is comparatively lower, making the assembly less prone to severe warpage. Furthermore, since chip placement occurs at a later stage, known good dies (KGDs) can be pre-screened and selectively placed, thereby improving overall packaging yields. Consequently, the chip-last process is predominantly utilized for high-end chip manufacturing, such as in TSMC’s CoWoS platform.

Materials and equipment providers have developed several solutions to address warpage. On the materials front, using a glass substrate as an interposer can resolve warpage at its source, as the CTE of glass (approximately 2.6 ppm/°C) closely matches that of silicon. However, glass is prone to micro-cracking (a.k.a. “SeWaRe”) during processing, and the supporting supply chain ecosystem is still developing.

Related report: Intel’s No SeWaRe Glass Substrates: TGV Challenges and Advanced Packaging Supply Chain Role

Alternatively, adopting low-temperature curable photosensitive polyimide (PSPI) as the interposer material can reduce processing temperatures and thereby mitigate warpage. However, it remains a significant R&D challenge to formulate a material that simultaneously offers low-temperature curability, a low CTE, a low dielectric constant (Dk), and high rigidity.

Another materials-based approach involves applying an anti-warpage balance film during processing to neutralize stress differentials. This resolves the warpage issue without modifying the core packaging materials. However, AMC is the sole supplier of high-end balance films at the present.

On the equipment front, thermocompression and vacuum suction can suppress deformation at the surface level, while selective laser modification alters the localized molecular structure within the material to relieve stress. However, surface-level suppression carries the risk of elastic rebound caused by residual stress once the panel leaves the equipment station, while selective laser modification remains largely in the R&D phase.

Material Solutions for Warpage Control

Low-Temperature Curable PSPI

Low-temperature curable PSPI reduces thermal stress accumulation by curing at below 250°C, significantly lower than the 300–350°C required for conventional PSPI. However, developing PSPI that simultaneously offers low CTE, low Dk, and high rigidity remains a significant R&D challenge. Conventional PSPI typically has a CTE of 40–80 ppm/°C and a Dk in the 2.8–3.6 range, far from the properties of glass.

Currently, most low‑temperature curable PSPI suppliers are Japanese companies such as Toray and FujiFilm. As the semiconductor industry shifts toward localized sourcing, Taiwan-based vendors are actively developing competing products, though achieving low CTE, low Dk, and sufficient tensile strength remains a challenge.

Balance Film

Balance film is formed by coating a base film with a special adhesive. When laminated onto a glass carrier or EMC, it generates a compensating stress in the opposite direction to offset thermal stress accumulated during processing.

The usage timing of balance film in a Chip Last process is as follows:

1. The RDL is first built on the glass carrier. A laser release layer is coated on the carrier to facilitate later separation, with no warpage at this stage.

2. A layer of balance film is pre‑laminated on the underside of the glass carrier to introduce warpage into the glass carrier as pre‑compensation.

3. As the RDL is built up layer by layer, the pre‑compensated panel is gradually pulled flat by the stress of the RDL layers; the balance film is replaced as needed until both the chips and EMC are completed, at which point there should be no warpage.

4. A layer of balance film is pre‑laminated on top of the EMC before de‑bonding the glass carrier, to avoid severe warpage that would occur if the glass carrier were removed directly.

5. After ball drop, dicing is performed; once the panel stress is released by dicing, the balance film is then removed.

A complete process thus requires at least two balance films (laminated on the glass carrier and the EMC respectively), with additional films added as RDL layer count increases.

If an optical engine (OE) is incorporated into the package, balance film can first be applied on top of the PIC to compensate for its larger warpage, followed by bonding the PIC to the substrate and then the EIC.

Warpage control has become a defining challenge as PLP scales toward advanced AI chip packaging. For a full analysis on the supplier landscape, access our report: Deconstructing PLP Warpage: Low-Temp PSPI, Balance Films, and Supplier Analysis.

The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.