COMPUTEX 2026: Memory in Focus
From June 2 to 5, 2026, COMPUTEX 2026 kicked off in Taipei under the theme “AI Together,” with a focus on AI & Computing, Robotics & Mobility, and Next-Gen Tech. Memory is central to AI computing, and here’s what caught our eye on the show floor.
SK hynix - HBF & HBM & BlueField-4 STX
SK hynix presented a full product lineup covering the memory hierarchy for KV cache offloading (KV cache offloading will be explored in depth in our future article). At the G1 (GPU) tier, SK hynix displayed a schematic of its latest AI-N B (Bandwidth) product, which vertically stacks NAND to simultaneously achieve high memory capacity and bandwidth - also known as HBF (High Bandwidth Flash). In addition, SK hynix exhibited physical samples of each HBM generation from HBM2E through HBM4E.
At the G2 (System Memory) tier, SK hynix showcased its LPDDR5X and DDR5 product lines. At the G3 (Local Storage) through G4 (Network Storage) tiers, the company also exhibited its SSD product line.
Notably, targeting NVIDIA’s newly added G3.5 (Context Memory Storage) tier, SK hynix displayed the PE9010 M.2 and PEB210 E1.S SSDs designed for use in BlueField-4 STX.
Samsung Semiconductor - HPB & HBM5
Samsung Semiconductor debuted a physical mockup of its next-generation HBM5. Of particular note, Samsung is set to adopt its proprietary HPB (Heat Path Block) thermal architecture in HBM5 for the first time, designed to address heat buildup in the Base Die under high-bandwidth operation.
The key design highlight of HPB is the addition of a separate chimney-like thermal structure directly on the D2D PHY responsible for HBM-to-GPU data transfer, allowing heat to be conducted out directly, thereby reducing thermal resistance and improving operational stability. Similarly, SK hynix’s previously announced iHBM platform plans to stack ICE (Integrated Cooling Elements) directly on the D2D PHY, which is expected to reduce thermal resistance by more than 30%. These designs are expected to indirectly drive an increase in HBM Base Die area in future generations.
Samsung Semiconductor also exhibited physical Core Die and Base Die samples for HBM4E and next-generation HBM (HBM5). Notably, the HBM4E Base Die uses Samsung’s 4nm process, while the HBM5 Base Die is expected to make a generational leap to Samsung’s 2nm process.
In addition, the company showcased its AI memory portfolio across the KV cache memory hierarchy, including the HBM4 at the G1 (GPU) tier, LPDDR5X at the G2 (System Memory) tier, PM1763 SSD at the G3 (Local Storage) tier, PM1753 SSD at the G3.5 (Context Memory Storage) tier, and PM9D3a SSD at the G4 (Network Storage) tier - going head-to-head with SK hynix.
HANMI Semiconductor - HBM Fluxless TC Bonder
HANMI Semiconductor, the leading manufacturer of HBM TC Bonders, exhibited its Wide TC Bonder designed specifically for next-generation HBM (HBM5 and HBM6). In addition to supporting larger die areas, the Wide TC Bonder can be optionally configured with a Fluxless version to improve bonding accuracy, filling the gap between conventional TC Bonders and Hybrid Bonders.
PSMC - WoW (Wafer-on-Wafer)
Taiwan-based memory manufacturer PSMC (Powerchip Semiconductor Manufacturing Corporation) presented under the theme “3D AI Foundry,” collaborating with partners including AP Memory, Syntronix, ESMT, and A.I. Memory to build a fully integrated ecosystem spanning IP, IC design, foundry, OSAT, and end applications. One of the highlights was its WoW (Wafer-on-Wafer) 3D stacking technology.
Unlike ESMT’s aiPIM, which focuses on vertically stacking DRAM dies on top of a larger Logic Die, WoW technology stacks an entire Memory wafer on top of an entire Logic wafer, improving bonding efficiency.
PSMC’s group partner A.I. Memory, an IC design company focused on AI-in-Memory technology, showcased AIM 3.0, its first product to adopt Hybrid Bonding. Due to its vertical stacking design, the chip footprint is compact, making it well-suited for small Edge AI devices such as IP cameras, where real-time facial recognition is supported.
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