Advanced packaging has become one of the most closely watched battlegrounds in the AI chip supply chain. Back in May, we took a close look at some of the key bottlenecks, including SeWaRe micro-cracking in glass substrates and warpage in panel-level packaging. The industry is moving fast. TSMC continues to expand CoWoS capacity aggressively, while reportedly developing an “EMIB-like” approach of its own. Meanwhile, Intel’s EMIB-T has reportedly seen a significant yield improvement, intensifying the rivalry between the two advanced packaging heavyweights.

Against this backdrop, TrendForce maps out the latest developments in 2.5D and 3D advanced packaging, from the architectural differences between EMIB and CoWoS, to capacity trends, customer distribution, and what comes next as the industry moves toward panel-level packaging, glass substrates, and 3D stacking.

Chiplet Architecture: It All Comes Down to Interconnects

To understand why advanced packaging has become so critical, it helps to start with how chip design has been evolving.

As semiconductor nodes continue to shrink, transistor architecture has evolved in parallel. For instance, when semiconductor technology moved from 28nm to 16nm, the industry shifted from planar transistors to the FinFET (Fin Field-Effect Transistor) architecture. The next major transition begins at 2nm, marking the start of the GAAFET (Gate-All-Around FET) era.

Although the CFET (Complementary FET) architecture has already been developed for sub-1nm nodes, the cost of process scaling continues to climb. In response, IC designers have begun adopting a disaggregation strategy, breaking a single chip down into multiple chiplets. This means components that do not require extreme scaling are separated out, and only the core portions of the chip are shrunk further.

Realizing the full potential of a chiplet design depends on the interconnect quality between dies, which is precisely where advanced packaging comes in. By packing chiplets tightly together, advanced packaging enables high-bandwidth, low-latency interconnects.

Related report: The 2026 Semiconductor Inflection Point: Scaling from 2nm GAA to the Era of ASIC Sovereignty

2.5D Packaging: EMIB vs. CoWoS

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s 2.5D advanced packaging technology. It integrates two sequential processes: CoW (Chip-on-Wafer), in which multiple dies are bonded onto a silicon interposer via micro-bumps, and oS (on-Substrate), in which the interposer is subsequently bonded onto the package substrate.

At 2026 OCP APAC Summit, TSMC stated that its 5.5x reticle size CoWoS is now in volume production, with yields consistently topping 98% across multiple AI customer products and reaching as high as 99% in some cases. The company expects to scale beyond 14x reticle size by 2029.

The key difference between Intel’s EMIB and CoWoS lies in the interposer. EMIB embeds a silicon bridge directly into the substrate to serve as the communication link between chips, eliminating the need for a full-size interposer and reducing cost as a result.

Assuming comparable yield stability between the two, Intel’s EMIB architecture offers lower cost potential than TSMC’s CoWoS by design. As for reticle size, Intel previously noted that its EMIB-T will scale to more than 8x this year and beyond 12x by 2028.

Although performance and reliability at scale have yet to be fully validated, the technology has already attracted interest from major ASIC vendors. At its 2026 Q2 earnings call, Intel CEO Lip-Bu Tan said the company is now focused on ramping EMIB-T into high-volume production to support customer ramps in 2027.

Taiwan’s OSAT providers have also been moving quickly in 2.5D packaging. ASE’s Fan-Out Chip on Substrate (FOCoS) uses multiple RDLs to integrate processors, memory, and I/O chips, with RDL layer counts scaling from 3 or 6 layers up to as many as 12. According to the company, this delivers interconnect density roughly 50x that of traditional flip-chip packaging, and over 200x with FOCoS-Bridge. SPIL, meanwhile, has developed FOEB (Fan-Out Embedded Bridge), which embeds silicon bridges within the RDL layer to enable near-monolithic, high-density, short-reach connections between dies.

Related report: Foundry Market Bulletin - Aug. 17, 2026

Behind the paywall, we explore:

• EMIB vs. CoWoS full spec comparison and key customers

• CoWoS capacity share among major customers

• Updates on glass-based solutions and 3D/3.5D packaging

• TrendForce view on overall supply and price trends

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This year, the Chinese government has actively encouraged the adoption of domestic AI chips. This policy push will likely provide priority support to high-potential domestic players, allowing them to substantially expand their market share in China’s high-end AI server market. At the same time, the domestic ecosystem is maturing in key areas such as advanced foundry nodes, advanced packaging, and thermal management. Together, these developments are moving China’s AI infrastructure away from its heavy reliance on foreign GPUs, toward a dual-track model of “domestic GPUs + proprietary ASICs.”

This article will explore:

• How China’s high-end AI chip supply structure is being reshaped

• WAIC 2026: The shift toward rack-scale supernode architectures

• TrendForce View on component demand driven by supernode architectures

Related report: Global Capex Rises as China Builds AI Autonomy

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In June 2026, the US Department of Defense added Unitree to its Section 1260H list of “Chinese Military Companies”. On July 28, the US Federal Communications Commission (FCC) announced plans to restrict imports of new foreign-made humanoid and quadruped robots. The move is driven not only by national security concerns but also by an effort to boost the development of America’s own advanced robotics industry. Widely interpreted as targeting China, it begs an obvious question: just how critical a role does China actually play in the global supply chain?

Related report: US Restrictions on Humanoid Robot Imports Temporarily Curb Chinese Competition While Driving Long-Term Supply Chain Restructuring

Policy Initiatives and the Industry Ecosystem for Humanoid Robots in China

China’s humanoid robot industry entered a phase of rapid growth in 2025, with companies such as Unitree and AgiBot each shipping over a thousand units that year. According to TrendForce, China’s 2026 production volume is expected to account for nearly 70% of the global total. Driven by government policy, the industry is moving toward standardization and use-case segmentation, facilitating subsequent model training and data collection while providing a cohesive framework for industry development.

At the same time, China is deploying state-backed capital to subsidize the development of the robotics sector, while promoting open-source frameworks to incentivize the sharing of technologies and research outcomes, reducing redundant R&D expenditures. Technologically, these policies explicitly target three foundational pillars: embodied AI models, motion control algorithms, and core hardware components, systematically cultivating a comprehensive industry ecosystem.

In terms of product development, China currently concentrates on general-purpose functionality, which requires robots to operate across multiple scenarios and tasks. This calls for hardware specifications with mature motion control, environmental sensing, and recognition capabilities, combined with large AI models and highly efficient, low-latency computing, to approach human-like reaction speeds and intelligent behavior.

However, at the current stage, limited production capacity and high unit costs make it difficult to deploy humanoid robots at scale for data collection in the near term. Compared to household environments, which involve high use-case diversity and extreme privacy sensitivity, structured settings such as logistics warehouses and factory floors offer greater environmental controllability and easier data access, making them the primary deployment scenarios at this stage.

Below, we will explore:

• Why the shift from extreme performance to practical reliability is changing what key components need to deliver

• How China is targeting the movement and power planes as its breakthrough point for domestic substitution, with a supply chain breakdown

• TrendForce’s view on what it will really take for China to scale up

Related report: Development of China’s Humanoid Robot Industry: Supply Chain Self-Sufficiency and Challenges for Key Components

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For instance, researchers have rethought how many Key-Value vectors a model actually needs to keep around. Alongside that, a separate line of work has asked whether those vectors need to be stored at full precision at all. But even when KV Cache’s capacity requirements are lower, it can still be slow to read. Some companies are tackling this bandwidth problem directly, rethinking how models generate tokens in the first place.

Behind the paywall, we break down:

• How Google and DeepSeek reworked attention mechanisms via GQA and MLA

• How NVIDIA’s KVTC and Google’s TurboQuant quantize KV Cache down to a fraction of its size

• How Google, Meta, and DeepSeek are racing to fix the decode bandwidth bottleneck, from MTP to DiffusionGemma

• TrendForce View: what solving the KV Cache bottleneck means for memory demand

Related report: Overcoming the Memory Bottleneck: CXL Expansion and KV Cache Compression Innovations

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Chipmakers, CSPs, and infrastructure vendors are now converging on the problem from opposite ends. Part 1 of this series looks at capacity expansion: how CXL technology and KV Cache offloading are creating a new tier in the memory hierarchy, and which companies are positioned along the way. Part 2 looks at footprint compression, where attention mechanism improvements and KV Cache quantization shrink how much room the KV Cache needs in the first place.

Why KV Cache becomes the bottleneck

If you read our previous article on AI memory, you will recall that the KV Cache is a dedicated memory space used during inference to store the KV (Key-Value) vectors generated in the prefill phase. By reading from the KV Cache instead of recalculating those vectors at every decode step, AI models dramatically improve inference efficiency.

The catch is that the KV Cache is dynamically allocated. Its memory footprint scales with both the context window and the batch size:

Total Size of KV Cache (Bytes) = 2 × layers × KV heads × head dimension × sequence length × batch × precision (Bytes)

Consider Llama 3 70B loaded in FP16 without GQA (using standard MHA). The model weights occupy roughly 140GiB, so early on, most of the available memory capacity is used to store the weights. But as the context window scales (assuming batch size of 1), the KV Cache consumes 160GiB at 64K, already exceeding the memory capacity required for the model weights. At 128K, it swells to 320GiB, roughly 2.3 times the size of the model weights. KV Cache becomes the primary driver of memory exhaustion.

Behind the paywall, we dig into capacity expansion solutions designed to resolve the KV Cache bottleneck:

• The mechanics behind CXL

• Enfabrica’s EMFASYS

• Penguin Solutions’ MemoryAI KV Cache Server

• Marvell’s Structera S

• Meta’s Vistara and MemServer

Related report: Overcoming the Memory Bottleneck: CXL Expansion and KV Cache Compression Innovations

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This piece is written for readers looking to build a clear, foundational understanding of AI memory requirements.

Contents:

1. Memory requirements for AI training

2. Memory requirements for AI inference

3. How the memory structure changes as the industry moves from training to inference

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Memory Requirements for AI Training

AI training refers to the process of using a training dataset to teach an AI model new capabilities. AI inference refers to the process of applying an already-trained model to new data to generate a response. Because these two stages require very different types of memory, memory architecture has diversified rapidly in recent years.

Taking today’s dominant Transformer architecture as an example, the training process consists of three main stages:

1. Forward Pass: The weights of each layer are read from memory into the compute die, where large-scale matrix multiplication produces a predicted output. A loss function then compares this output against the correct answer to measure the error (loss).

2. Backward Pass: Following the chain rule, the model reads the activations temporarily stored during the forward pass, layer by layer, and computes gradients that match the size of the weights.

3. Optimizer Update: After reading the gradients, the model updates and writes back the weights themselves, along with two optimizer state tensors of the same size as the weights (first-moment m and second-moment v).

Because the model must repeat these three stages over and over to minimize loss and converge, memory access speed becomes the key factor determining training efficiency.

This is the context in which HBM (High Bandwidth Memory) emerged: multiple layers of DRAM stacked vertically and connected via TSV. Unlike conventional DRAM, which connects over relatively slow PCIe (PCIe 6.0 x16 offers 128 GB/s of unidirectional bandwidth), HBM is packaged side by side with the compute die on the same interposer, shortening the data path. A single HBM stack can deliver more than 2 TB/s of bandwidth (HBM4 offers over 1 GB/s per pin in one direction across 2,048 pins), which has significantly accelerated the industrialization of AI.

The memory hierarchy gained a new tier, HBM, during the training era, filling the gap between on-chip SRAM and conventional DRAM.

Related report: 3Q26 HBM Datasheet

Memory Requirements for AI Inference

AI inference consists mainly of two stages:

1. Prefill: The input prompt is processed in parallel in a single pass. The Key and Value vectors for each layer are computed and stored in memory (the KV Cache), and the first output token is generated at the same time.

2. Decode: Key and Value vectors are read from the KV Cache to generate tokens one at a time, while newly computed Key and Value vectors are continuously written back into it, until the response is complete.

Because the Decode stage requires repeated token-by-token reads and writes to the KV Cache, and because KV Cache size keeps growing with the number of conversation turns, context window length, and batch size, relying on HBM alone is increasingly insufficient to keep up with growing inference demand. Memory capacity has become a second critical bottleneck, alongside bandwidth.

Unlike the relatively mature memory architecture built for AI training, AI inference memory architecture is only now developing rapidly alongside test-time scaling. Vendors are still actively experimenting with different memory approaches, and the memory hierarchy is in the middle of a paradigm shift.

To address the growing capacity needs of KV Cache, memory makers SanDisk and SK hynix announced a partnership in August 2025 to develop HBF (High Bandwidth Flash), which stacks multiple layers of NAND vertically and connects them via TSV. At an expected bandwidth of 1.6 TB/s, a single HBF stack is projected to offer around 512 GB of capacity, roughly ten times or more that of HBM (a 16-Hi HBM4 stack offers 48 GB), filling the gap between HBM and conventional DRAM.

While HBF has yet to reach mass production, many vendors are concurrently using KV Cache offloading to move less frequently used KV Cache down to lower tiers of memory, easing the burden of storing large volumes of KV Cache. In this context, NVIDIA introduced the concept of SSD POD in 2026, filling the gap between local SSD and shared storage.

Notably, beyond HBF and SSD POD, some inference ASIC startups have introduced high-speed SRAM to break past HBM’s speed limits. Groq (whose inference technology license and core team were secured by NVIDIA in December 2025) and Cerebras, for example, use large areas of on-chip SRAM to significantly increase decode speed.

Related report: 2026 Trends: Memory for New AI Inference Demand

Memory Structure Changes from Training to Inference

In the first half of 2026, as inference demand continued to surge, NVIDIA announced it will incorporate the Groq LPX chip into its Rubin series, expected to be available later this year, alongside the introduction of CMX (Context Memory Storage Platform) and the Vera CPU Rack.

Google also unveiled the TPU v8i, designed specifically for inference, which carries 72 GB more HBM3e and 384 MB more SRAM than the TPU v8t, which is designed for training.

Beyond these two major players, a number of AI ASIC startups building inference-specific chips have been active in the first half of 2026: SambaNova launched its fifth-generation chip, the SN50, in February 2026; Cerebras filed for an IPO in April 2026 and announced partnerships with OpenAI and AWS; and Etched announced in June 2026 that its Sohu chip had successfully taped out at TSMC.

Looking at how the training era was dominated almost entirely by HBM, compared with the far more varied inference landscape today, the design choices for the memory hierarchy can be expected to keep diversifying going forward.

Coming up next

In our next piece, we take a closer look at how industry leaders are turning to CXL expansion and KV Cache compression to address the memory bottleneck, along with what this means for the memory market going forward. Subscribe so you don’t miss it.

Contents:

1. China’s ultra-bionic robot boom, and the companion economy behind it

2. Why the US is betting on AI while China bets on scale

3. Who really controls the supply chain, mapped out with our new CSCII index

China’s Ultra-Bionic Robots Open a New Companion Economy

As generative AI matures and social trends such as aging populations, falling birth rates, and rising numbers of single-person households reshape demand, robots are shifting from labor substitutes to emotional companions, driving rapid development in China’s ultra-bionic humanoid robots. Unlike traditional humanoid robots that emphasize bipedal walking, lifting, and task execution, these products prioritize lifelike appearance, emotional expression, and natural interaction, aiming to build long-term human-robot relationships. China’s market currently features diverse technical approaches. For instance, AheadForm’s Origin F1 focuses on eye contact, micro-expressions, and a desktop half-body design, using a high degree of facial articulation to reduce the uncanny valley effect. Noetix Robotics’ Hobbs 3 Series targets the desktop companion market, emphasizing synchronized voice and expression, emotional interaction, and family companionship.

Related report: Humanoid Robot Quarterly Report - 3Q26

Unlike most ultra-bionic robots, which use half-body or fixed designs, UBTECH’s UWORLD U1, launched in June 2026, is a full-size humanoid. It combines highly realistic silicone skin, 88 degrees of freedom, a biomimetic cervical spine, and full-body motion control, enabling not only natural facial expressions but also more realistic interaction through complete body movement. On the AI side, it incorporates an emotion-aware LLM that integrates long-term memory, multimodal perception, voice interaction, and on-device AI inference, allowing it to adjust dialogue and interaction style based on the user’s emotional state. TrendForce observes that China’s ultra-bionic humanoid robots are gradually expanding into companionship, entertainment, elder care, and digital content applications, with competition shifting from hardware performance to emotion AI, content services, and overall user experience.

For the supply chain, beyond existing humanoid robot components such as servo motors, reducers, and dexterous hands, demand is also expected to grow for high-fidelity silicone materials, electronic skin, multimodal sensors, microphone arrays, vision modules, edge AI chips, and emotion models, giving rise to a new industry ecosystem that combines mechanical, AI, and consumer electronics characteristics.

US-China Divergence: Intelligence vs. Scale

• US: Deepening the AI Ecosystem, Shifting Value from Hardware Specs to Intelligence

The AI ecosystem remains the US’s greatest advantage in humanoid robotics. As generative AI, Vision-Language-Action (VLA) models, and world models mature rapidly, the value of humanoid robots is shifting from hardware specifications to intelligence. Major players such as NVIDIA continue to advance Physical AI platforms including Cosmos, Isaac Lab, and GR00T; Google DeepMind has launched Gemini Robotics to strengthen robotic understanding; and OpenAI is participating in embodied AI model development through investment and research. Together, US firms are forming a complete technology ecosystem spanning large language models, robotics platforms, simulation environments, and AI chips. This reflects the view that as humanoid robots move into complex environments, competitiveness will depend on environmental understanding, multi-step task planning, cross-scenario generalization, and continuous learning.

US companies’ strategies have also shifted from demonstrating hardware capability to building AI capability. Tesla‘s Optimus Gen 3 continues real-world validation on factory floors, with future production focused on improving the robot’s generalization so the same AI can quickly adapt to different work environments. Figure AI is deepening partnerships with large enterprises to train its models on large volumes of real factory data. Boston Dynamics combines years of motion control expertise with AI to strengthen autonomous operation in complex environments. Apptronik generates high-quality data through extensive real-world deployment, feeding it back into the Gemini Robotics training pipeline.

In short, US firms are focused on building a data flywheel, aiming to continuously refine their models with large volumes of real-world data and differentiate their products through AI capability.

• China: Accelerating Supply Chain Integration, Shifting from Product Iteration to Scale Deployment

By contrast, China’s humanoid robot development more closely resembles the early development model of electric vehicles: building a complete supply chain and lowering costs quickly, then achieving economies of scale through high shipment volumes. Under this approach, core components such as servo motors, reducers, and lithium batteries can be localized quickly, lowering costs and significantly shortening development cycles.

The two most representative companies are Unitree and AgiBot: Unitree has built a reputation for high value for money and rapid product iteration across both quadruped and humanoid robots, while AgiBot scaled its production from 1,000 to 5,000 units in about a year, and then from 5,000 to 10,000 units in just three months. This shows that China’s advantage today extends beyond manufacturing cost. Its supply chain maturity allows new products to complete component validation, pilot runs, and mass production quickly, giving it a faster iteration pace than its Western competitors.

Notably, as factories, logistics operations, and public venues continue to adopt humanoid robots, China is rapidly accumulating real-world data through large-scale deployment, extending its supply chain advantage into a data advantage. This could help China’s humanoid robot industry form a positive cycle of “deploy, collect data, update the model, redeploy.“ As models continue to improve, the AI gap between China and the US may narrow as a result of China’s data scale.

Supply Chain Power: Component Cost Breakdown and the CSCII

As the humanoid robot industry rapidly takes shape, “who controls the supply of key components” has become a core question in assessing each region’s industrial competitiveness. TrendForce has designed the Component Supply Chain Influence Index (CSCII) to systematically analyze how well each region’s suppliers control different key components.

The CSCII is a composite indicator combining qualitative and quantitative assessment; it is not a single, directly verifiable statistic. Ratings are weighted across five dimensions using expert judgment:

1. Industry scale position: measuring a component’s global revenue share across industries, reflecting manufacturing scalability.

2. Technology barriers and substitutability: measuring patent concentration and how quickly followers can catch up.

3. Humanoid robot application penetration: measuring the breadth of actual design-in by mainstream OEMs in humanoid use cases.

4. Production capacity and expansion momentum: measuring supply flexibility and manufacturing scaling speed.

5. Policy and geopolitical supply resilience: factoring in export control exposures and domestic policy support.

Let’s break it down by region:

• China has the most comprehensive presence across all four planes, leading the Power Plane and rated “Strong” in both the Mental and Movement Planes, with its strength built on manufacturing scale and broad component coverage.

• The US holds the most pronounced leadership in the Mental Plane, where NVIDIA and Qualcomm command a near-monopoly in AI chips and computing platforms.

• Europe is rated “Strong” in both the Sensing and Movement Planes, with its strength concentrated in precision manufacturing. Its companies are less well known than major players in other regions, but carry deep technical value, with German suppliers holding a distinct edge in encoders.

• Japan holds a solid lead in the Movement Plane, and its strength is highly concentrated in mechanical transmission, where companies have established deep technology barriers.

• South Korea is currently rated “Strong” in the Power Plane, supported by active battery investments from LG and Samsung. Other planes will depend on stronger public-private collaboration to accelerate ecosystem development.

TrendForce View

As the humanoid robot industry moves toward commercialization, companies are shifting their focus from the novelty of product iteration to the durability of their business models. The US and China are pursuing two distinctly different competitive strategies: the US is emphasizing AI, large models, and high-value applications to make its products smarter, while China is leveraging its full manufacturing ecosystem and supply chain advantages to accelerate product iteration and scale deployment.

China’s rapid rise is putting real pressure on US manufacturers today. But over the long run, what will determine the global humanoid robot industry’s landscape is whether companies can build business models that combine scale deployment, data accumulation, and sustainable profitability for their target markets. Given the diversity of commercial use cases and user needs, TrendForce believes that the future market is unlikely to be winner-take-all — multiple players are likely to coexist.

China’s path in the robotics industry is a complex story on its own. In Part 2, we’ll look at how Chinese manufacturers are borrowing from the electric vehicle playbook to localize key components. Subscribe so you don’t miss it.

From a CapEx perspective, North American cloud service providers (CSPs) have significantly raised their 2026 capital expenditure guidance, with investment increasingly concentrated in the deployment of high-performance GPU clusters, in-house ASIC development, and next-generation data centers designed to support high-power-density computing.

In China, leading CSPs such as ByteDance and Alibaba are making equally substantial commitments to compute infrastructure. The continued rollout of the East Data West Computing (EDWC) initiative (which redirects eastern computing workloads to western regions to optimize data center distribution and promote balanced regional development) has positioned AIDCs as a core link between the digital economy and the modern power grid.

However, the three defining characteristics of AIDCs — high power density, extreme load volatility, and massive energy consumption — place immense pressure on power systems. To ensure the stable operation of compute workloads, energy storage systems have evolved from an “optional add-on” to “mission-critical infrastructure.”

The following analysis covers energy storage demand dynamics across North American and Chinese markets, as well as the energy storage solutions offered by major Chinese manufacturers. Insights on the Chinese market draw on TrendForce’s ongoing primary research and long-term coverage of the local industry.

North America and China: Different Challenges, One Common Need

The enormous power demands of AIDCs are driving regional grid loads sharply higher, widening energy supply gaps. North America and China face distinct challenges, but both are accelerating energy storage deployment as a result.

• North American Market: Grid Constraints and Gas Turbine Shortages Drive Urgent Storage Demand

North America is a core hub for global AIDC development, with electricity supply heavily dependent on natural gas — gas-fired generation accounts for 40–50% of the energy mix across most regions. Surging AIDC power demand has further tightened large gas turbine supplies. Faced with growing supply-demand imbalances and an escalating risk of grid outages, AIDC operators are under pressure to increase their share of renewable energy generation. However, the inherent intermittency and volatility of solar and wind power mean that robust energy storage systems are essential to guarantee 24/7 uninterrupted data center operations.

• Chinese Market: Policy Support and Resource Optimization Accelerate Storage Integration

China’s AIDC build-out is driven by national strategic initiatives, with optimizing regional resource allocation at its core. The government has incorporated “Computing-Power Synergy” (the coordinated planning of AI compute infrastructure and power systems) into new infrastructure projects, encouraging compute facilities to deploy advanced and grid-forming energy storage systems.

In practice, power grids in China’s eastern compute hubs are approaching their load capacities, while grid infrastructure in renewable-rich western regions remains relatively fragile. Ultra-high-voltage (UHV) transmission networks alone cannot fully mitigate the pulsed load shocks generated by AIDCs. Coupled with regulatory requirements for green electricity consumption, grid-forming energy storage and long-duration energy storage (LDES, predominantly 4–8 hours) have consequently become standard configurations for compute hubs, further accelerating the pace of energy storage integration.

Related report: Mutual Empowerment of AI Computing Power and Electricity: Power Grid, Long-Duration Energy Storage, and New Power System Transformation

AIDC Storage Demand on Two Fronts

AIDC energy storage is primarily deployed across two domains: the data center side and the generation side. On the data center side, during Large Language Model (LLM) training, AIDCs experience severe, pulse-like power transients that place extreme demands on power continuity and grid resilience. To address this challenge, NVIDIA's 800V DC architecture white paper highlights the need for a layered storage approach, leading to a two-tier deployment: external (facility-level) and internal (rack-level) storage.

• External (Facility-Level) Storage serves as reliable backup power, keeping grid load volatility under 2%; BESS can also participate in grid peak shaving and ancillary service markets. Additionally, they provide essential frequency regulation for on-site captive generation such as gas turbines and nuclear reactors.

• Internal (Rack-Level) Storage addresses immediate power anomalies within the facility. BBUs leverage DC-DC conversion for high efficiency, low parasitic power draw, and a compact form factor, suitable for distributed integration directly inside high-power-density AI server racks. Supercapacitors complement this by enabling instantaneous discharge of massive electrical transients with near-zero energy loss.

Related report: NVIDIA AI Server Power Roadmap & Data Center Build Risk

On the generation side, as the costs of solar modules and energy storage systems continue to decline, the levelized cost of energy (LCOE) for solar-plus-storage has fallen below that of conventional generation sources such as natural gas and nuclear power, giving solar-plus-storage a distinct cost advantage. As the green electricity transition accelerates AIDC adoption of renewable energy globally, energy storage systems play a critical role in ensuring stable alignment between variable renewable supply and the continuous, high-load power demands of data centers.

China’s Energy Storage Supply Chain: Accelerating Cell and Systems Technology Upgrades

This wave of AIDC-driven demand is accelerating technology development among Chinese energy storage manufacturers.

• Cell technology is advancing toward higher reliability, efficiency, and safety.

• Systems technology encompasses grid-forming storage, high-voltage DC (HVDC) architecture, liquid cooling, and long-duration energy storage.

TrendForce View

The global energy storage market in 2026 is entering a new phase of demand restructuring driven by AIDCs. Across the value chain, solar, wind, and storage are integrated on the generation side; grid-forming storage supports the grid side; and layered BESS, BBU, and supercapacitor protection covers the load side. At the dispatch level, AI-powered energy management systems (EMS) enable real-time matching of computing load and power supply. Together, these form a new type of infrastructure defined by the efficient synergy of computing power, electric power, and energy storage.

TrendForce believes that AIDCs will continue to provide steady growth momentum for the energy storage sector. Energy storage will play an increasingly critical role in securing compute reliability and advancing energy transition.

For an in-depth analysis and vendor breakdown, access our full report: 2026 Energy Storage Turning Point: AIDC Fuels Dual-Engine Demand Growth

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Against this backdrop, the competitive landscape for ASIC design and service providers is also changing. This article examines how NVIDIA and major CSPs are positioning themselves at the AI rack/POD scale, and how ASIC designers, including Broadcom, Marvell, MediaTek, Global Unichip (GUC), and Alchip, are leveraging interconnect technologies such as CPO to expand their reach from chip scale into the rack/POD scale arena.

Related report: AI Interconnect Outlook: NVIDIA Leads the Transition to CPO and Silicon Photonics Architectures

NVIDIA Expands Beyond the Chip to Every Layer of AI Infrastructure

First, a quick definition: an AI POD (Point of Delivery) is a standalone AI computing unit composed of compute nodes, networking, storage, and software. Scale-up interconnect (vertical scaling within a single system) is the technology that enables multiple chips, and even cross-rack configurations, to operate as a single unified system with ultra-low latency, forming the foundation for Rack/POD-scale integration.

As the primary unit of AI computing continues to expand, NVIDIA unveiled not only seven new Rubin-series chips at its March 2026 GTC, but also five MGX-series racks capable of integrating these chips into a single rack, and racks can be interconnected via switches to form a large-scale Vera Rubin POD.

To further strengthen its AI data center hardware portfolio, NVIDIA has in recent years secured key talent and technology licenses from memory-interconnect switch IC vendor Enfabrica and AI inference LPU vendor Groq, while also investing in quantum computing and optical-communication component suppliers, all in pursuit of pushing POD-scale performance to the extreme.

Related report: NVIDIA FY1Q27 AI Server Outlook: GB/VR Rack Leads

Google, AWS and Microsoft Build Proprietary AI Rack/POD around Efficiency

To improve AI computing performance, CSPs are not only adopting large on-chip SRAM in their inference chips, but also designing proprietary AI racks and PODs. Google has been the most aggressive, adopting its own scale-up technology ICI (Inter-Chip Interconnect) as early as 2017, introducing OCS (Optical Circuit Switch) in 2021, and planning to deploy its in-house Axion CPU and Boardfly network architecture in the TPU v8 series in 2026.

AWS plans to deploy its proprietary NeuronLink and Graviton CPUs in the 2026 Trainium3 UltraServers, while Microsoft plans to deploy an Ethernet scale-up network and Cobalt 200 CPUs in its Maia 200 POD. Meta takes a different approach entirely, adopting the open OCP (Open Compute Project) standard to build a standardized data center hardware ecosystem aimed at reducing overall costs.

Related report: 2026 AI Server Outlook: CSP Rack Power Scales Up

ASICs: Broadcom and Marvell lead; MediaTek, GUC and Alchip bet on CPO

The trend of CSPs independently designing AI racks/PODs has pushed ASIC design and service providers to expand beyond chip-scale offerings into rack/POD-scale solutions. For ASIC designers, this creates an entirely new incremental market.

Broadcom and Marvell have already built out comprehensive product lines spanning switches and NICs, while also taking an early lead in CPO technology. MediaTek, GUC, and Alchip are initially focusing on establishing strong track records in AI chip development, with plans to leverage CPO integration platforms as their path into the rack/POD scale market.

As shown in TrendForce’s product line overview, CPO is the technology track, aside from AI chips, that all six major companies have committed to investing in, signaling broad industry recognition that CPO has become one of the critical differentiators for next-generation AI rack/POD performance.

For an in-depth analysis of each vendor’s strategy and product roadmap, access our full report: ASIC Design and Service Competition Shifts from Chip Scale to Rack/POD Level.

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Apple’s entry in 2026 is expected to reinvigorate the foldable market. TrendForce estimates that Apple, leveraging its strong brand positioning and consumer anticipation, could capture nearly 20% market share in 2026, compressing the share of competitors such as Samsung Electronics and Huawei to around 30% each.

As for the technology itself, the competitive focus is shifting beyond hinge mechanics and structural optimization toward materials science. Foldable devices are entering a critical phase on the path toward creases that are truly imperceptible.

Related report: Quarterly Smartphone Market Status Update - 2Q26

From Foldable to Creaseless: Three Phases of Development

From Samsung’s crease-free display panel showcased at CES 2026 to OPPO’s recently launched Find N6, marketed around a “virtually crease-free” design, the industry’s appetite for a genuine breakthrough is clear.

Creases originate from the misalignment of the neutral layer within the panel stack, which causes localized tensile stress, leading to micro-cracks or permanent deformation under stress concentration. Solving this problem has driven the industry through three distinct phases of development.

Phase one (2019-2022): feasibility verification

The central question at this stage was whether a foldable device could fold reliably. Technical efforts focused on panel durability and hinge lifetime. Early products commonly used U‑shaped hinges, which forced the panel into a small bending radius when folded, causing strong stress concentration and deeper, more visible creases.

This then evolved into water drop hinge design, which increased the bending radius to distribute stress more evenly, significantly improving both panel lifetime and crease performance. Some manufacturers also introduced dual-track floating support structures that brace the panel from beneath when unfolded, helping the display lie flatter.

Phase two (2023-2025): structural optimization

At this phase, the focus was mass production and reliability improvement, with the goal of simplifying mechanisms and upgrading materials to improve assembly yield and overall product durability.

On the mechanical side, smartphone brands gradually reduced the number of components, optimized assembly processes, and introduced techniques such as welding, mortise-and-tenon joints, and 3D printing to improve overall production quality and consistency. On the materials side, they moved beyond traditional SUS stainless steel to aerospace‑grade alloys, carbon fiber, and reinforced composites, and began experimenting with novel materials like liquid metal to better balance strength and weight, enabling thinner, lighter, yet more durable product designs.

In addition, unified specs and design languages emerged: water drop hinges became the mainstream structural solution, clamshell and in-folding emerged as the two primary form factors, and key mechanisms such as sliders and cantilever supports settled into relatively fixed design architectures.

Phase three (2026~): material dominance

By 2024-2025, mechanical optimization had gradually approached its limits. Water drop hinges, floating supports, and multi-link designs — even with ever-higher precision — could make creases less noticeable, but could not make them truly disappear. This pushed the industry to rethink the problem at its core: a crease is not merely a structural issue, but the result of material deformation and fatigue under repeated stress.

Therefore, starting in 2026, the industry has shifted its focus toward materials engineering to actively regulate stress distribution and prevent bending stress from concentrating in a single region.

The crease problem is gradually moving from a visible defect toward something almost imperceptible — laying the foundation for a truly mature foldable product.

So what is actually driving this materials-led transformation? The answer lies in two key materials: UTG and OCA.

UTG: From Protective Layer to Core Mechanical Component

In the past, UTG was primarily used as a surface protective material, providing hardness, scratch resistance, and tactile feel. In next-generation foldable devices, it has become the structural core that defines how stress is distributed across the display stack.

The key design shift starts with thickness redistribution. Traditional homogeneous glass applies a single thickness across the entire panel, forcing a trade-off between strength and flexibility. Under a non-uniform thickness design, the folding area is precisely thinned to improve flexibility and reduce stress concentration, while non-folding areas maintain a greater thickness to preserve rigidity and impact resistance.

This design philosophy is also reflected in Apple’s foldable device patents.

Through chemical strengthening and multi-layer surface coatings, UTG’s resistance to cracking and fatigue has significantly improved, maintaining structural integrity under repeated folding. That said, UTG remains a high-modulus material whose primary function is to guide stress, not absorb it. Without an intermediary layer capable of absorbing and regulating stress, localized forces can still accumulate at layer interfaces, compromising long-term reliability.

OCA: From Adhesive Layer to Critical Stress Manager and Optical Interface

That intermediary layer is OCA (Optically Clear Adhesive). Once used primarily as an optical adhesive material for display modules, OCA has taken on a far more active role in next-generation foldable displays: dynamically distributing and buffering stress between material layers.

The key lies in the precise design of the material’s viscoelasticity, enabling it to exhibit distinctly different mechanical behaviors under varying strain conditions and time scales. During normal, gradual bending, OCA maintains a lower modulus, staying soft and allowing the stack to conform to deformation while absorbing stress, thereby reducing both fatigue accumulation and micro-crack formation. Under sudden impact, such as a drop or localized press, its modulus temporarily rises to provide structural support and prevent stress from concentrating in any single layer. The result is a material that is soft under everyday use and stiff when it needs to be.

Through these mechanisms, OCA helps stabilize the neutral layer and significantly reduce stress concentration during folding. Its micro-flow characteristics also allow it to fill microscopic irregularities formed over long-term use, reducing light scattering and further minimizing the visible crease.

TrendForce View

While material innovation now leads crease reduction, mechanical structures remain critical. The OPPO Find N6, for example, uses precision machining and 3D printing technologies to enhance hinge flatness, while polymer materials fill structural gaps to prevent localized suspension and stress concentration, ensuring stable deformation during repeated folding. Meanwhile, for the metal support plate behind the display, Samsung Display has adopted laser drilling technology to reduce hole spacing in bending areas, achieving a balance between structural rigidity and flexibility, and enabling a near crease-free visual experience.

Essentially, the key to crease improvement has shifted from hinge design to the coordinated management of material modulus, thickness distribution, and stress release. Only when unfolding leaves no trace will foldable phones truly reach the mainstream.

For a deeper dive into material stack design and foldable market forecasts, access the complete analysis here: Last Mile for Folding: Revolution of Crease from Mechanical Structures to Materials Science

In May 2026, Samsung Electro-Mechanics announced a silicon capacitor supply contract worth approximately USD 1 billion with a major global customer, covering deliveries through 2027 and 2028. A month later, the company outlined its strategic direction, pointing toward an integrated approach that bundles silicon capacitors, MLCCs, and package substrates. This reflects a broader market trend: silicon capacitors are emerging as vital complementary components for package-level power integrity.

What roles do silicon capacitors and MLCCs each play in power integrity, and how do they complement each other? This article examines the technical characteristics of both, and the supply chain dynamics.

Related report: MLCC Market Outlook 1Q26~2Q26

Power Integrity Moves Inside the Package

As GPUs’ thermal design power (TDP) rapidly escalates, components such as power shelves, VRMs, DC-DC converters, and OAM boards require significantly more MLCCs for filtering and voltage regulation so as to prevent voltage ripples from compromising computational stability. In the meantime, as AI accelerator platforms evolve to incorporate chiplets, HBM, and high-density advanced packaging, power integrity challenges are no longer confined to the PCB level; they are penetrating deeply into the package itself.

In a multi-die architecture, a single GPU package might house a compute die, an I/O die, and an NVLink I/O die. Together with HBM, silicon interposers, and package substrates, these components form a highly dense system. Every individual die and power domain necessitates an independent, rapidly responding decoupling network. Relying exclusively on board-level MLCCs creates excessively long current paths, introducing parasitic inductance that severely throttles transient response speeds.

Silicon Capacitors’ Advantages

Manufactured using semiconductor fabrication processes, silicon capacitors utilize a silicon substrate paired with thin-film dielectric materials like silicon oxide or silicon nitride. Unlike traditional MLCCs—which generate capacitance through alternating layers of ceramic dielectrics and metal electrodes—silicon capacitors align more closely with semiconductor manufacturing principles. They leverage techniques such as thin-film deposition, deep trench structures, and customized packaging to increase capacitance per unit area while minimizing parasitic inductance.

The defining characteristics of silicon capacitors are their exceptionally low equivalent series inductance (ESL) and their ability to be placed in close proximity to the chip. During high-load operations, the current demands of AI GPUs, CPUs, ASICs, and HBMs fluctuate rapidly within fractions of a second; minimizing ESL ensures the capacitor can rapidly compensate for instantaneous power demands and maintain rigorous power stability, which is precisely the core value of silicon capacitors for near-die decoupling inside the package.

A further advantage of silicon capacitors is their superior capacitance stability across high frequencies, temperature variations, and DC bias. In environments with high DC bias or elevated temperatures, MLCCs utilizing certain material compositions often suffer from capacitance degradation or unpredictable fluctuations. By contrast, silicon capacitors—benefiting from silicon-based thin-film dielectrics and precise semiconductor manufacturing—deliver exceptional capacitance stability and dimensional accuracy. This makes them highly suitable for applications requiring high-density mounting, rapid high-frequency response, and unwavering capacitance.

Related report: NVIDIA FY1Q27 AI Server Outlook: GB/VR Rack Leads

Different Jobs, Different Layers

MLCCs serve as the primary components for system-level power stability in AI servers, offering unparalleled advantages in cost, supply scale, maturity, and mass deployment. As AI servers transition into the Rubin generation, the simultaneous increases in GPU power consumption, HBM density, NVLink bandwidth, and high-speed networking chip requirements will continue to drive the expansion of MLCC usage. TrendForce notes that while a single NVIDIA GB200 board requires approximately 6,500 MLCCs, the next-generation Rubin architecture—featuring double the TDP and significantly more complex power management—will push per-board usage to roughly 12,000 units.

Silicon capacitors, on the other hand, provide a high-end solution for package-level power integrity in AI accelerators, excelling in low ESL, ultra-thin profiles, high-frequency stability, and custom integration.

Depending on placement requirements, silicon capacitors can be configured in top-side, land-side, or embedded formats, and positioned alongside GPUs, CPUs, or ASICs, at the bottom of silicon interposers, or embedded within the package substrate itself. The closer the capacitor is to the die, the shorter the current loop and the lower the parasitic inductance, which is critical for suppressing transient voltage fluctuations and high-frequency noise.

The relationship between MLCCs and silicon capacitors should therefore be understood as complementarity, not substitution.

Supply Chain Dynamics

MLCCs mainly use traditional passive component processes, dominated by established players such as Murata, SEMCO, Taiyo Yuden, and Yageo. In contrast, the silicon capacitor supply chain is more closely aligned with semiconductor processes and advanced packaging. TrendForce believes that the core competency for silicon capacitor vendors lies in their ability to co-design with AI GPU, ASIC, HBM, and packaging platforms, and to pass qualification by high-end customers. Overall, silicon capacitors carry higher entry barriers and longer customer qualification cycles, and the supply scale remains relatively limited.

Outlook: A Dual-Track Future

The key to silicon capacitors’ future growth is not to completely replace MLCCs, but to ride the rising penetration of advanced AI packaging and gradually become standard components inside GPU, ASIC, and HBM packages. However, several challenges remain, including cost and supply scale, customer validation cycles, and a high degree of design binding.

In the long term, capacitor demand in AI servers will evolve into a dual-track structure of board-level MLCCs and package-level silicon capacitors. MLCCs will continue to benefit from rising per-rack power consumption and growing demand for high-capacitance and high-voltage products, while silicon capacitors will benefit from PDN upgrades inside AI accelerator packages, tighter HBM integration, and the proliferation of chiplet architectures.

For a full analysis of silicon capacitor technology, supplier dynamics, and market outlook, access our report: Power Integrity Upgrades in AI Servers: Evolving Roles of Silicon Capacitors and MLCCs.

To address the surging KV cache storage demands of the AI inference era, Nvidia introduced the CMX Context Memory Storage Platform in January 2026, managed by the BlueField-4 DPU, which adds a pod‑level context tier between local SSD and shared storage.

Meanwhile, the rise of Agentic AI is reshaping CPU architecture. Jensen noted that agents live in a world of nanoseconds, where every moment of waiting prevents them from advancing to the next step, making ultra-low latency the primary requirement. With Nvidia and Arm both launching CPU rack solutions purpose-built for agents, the industry is shifting from throughput-oriented to latency-oriented architectures, opening up an incremental market for CPU RAM.

Related report: Server DRAM Industry Analysis－2Q26

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MediaTek - CPO IP & LPO AOC

Taiwan’s leading IC design house MediaTek has been aggressively expanding into optical interconnect. After announcing a US$90 million investment in silicon photonics (SiPh) design firm Ayar Labs in February 2026, MediaTek showcased its latest solutions at COMPUTEX 2026 in June. The company demonstrated a CPO technology capable of reaching up to 400 Gbps per fiber to illustrate its scale-up roadmap, alongside a Micro LED LPO AOC sample developed in collaboration with Microsoft Research for scale-out connectivity.

The CPO chip sample on display features an EIC designed in-house by MediaTek, with the PIC co-developed with Ayar Labs. Each fiber delivers up to 400 Gbps, with an 8 x 400 Gbps configuration enabling a 3.2 Tbps optical engine (OE).

Related report: CPO Testing Challenges: TSMC COUPE & Taiwan Supply Chain

MediaTek also integrates Microsoft Research’s MOSAIC Micro LED technology to deliver an Active Optical Cable (AOC) featuring an integrated LPO transceiver. In this design, Micro LED serves as the light source within the LPO transceiver, with each Micro LED operating at 2 Gbps. Approximately 150 Micro LEDs are combined to achieve 200 Gbps aggregate bandwidth (with redundant units included to guard against localized failures).

The Micro LED approach offers a “wide-and-slow” light source with lower power consumption, lower cost, and higher reliability compared with conventional VCSEL and DFB lasers.

Related report: 2026 Infrared Sensing Application Market and Branding Strategies - Micro LED CPO Market Value Analysis

GUC & Wiwynn - CPO Rack

ASIC design service provider GUC has also been actively expanding its optical interconnect capabilities. Following its collaboration announcement with Ayar Labs in November 2025, GUC entered a partnership with Wiwynn and Ayar Labs in May 2026 to jointly develop a rack-scale CPO solution, which was showcased at COMPUTEX.

The CPO rack integrates Ayar Labs’ TeraPHY OEs and ELSFP SuperNova light sources, delivering 800 TB/s of scale-up optical bandwidth across 64 GUC ASICs (32 compute trays) per rack via CPO. It also incorporates a fully liquid-cooled thermal architecture developed in-house by Wiwynn.

Also notable: in addition to GUC and Ayar Labs, Wiwynn disclosed its broader CPO supply chain partners at the show. These include AI chip design services firm Alchip; Detachable FAU suppliers Corning, SENKO, Browave, and FOCI; ELSFP module and connector suppliers Molex, TE Connectivity, and SENKO; and Optical Cable suppliers AFL, Corning, SENKO, Molex, and FOCI. The CPO rack sample on display used SENKO’s ELSFP module, Optical Cable and SN-MT connector.

Largan & AOET - PMLA & FAU

Largan Precision, the global leader in smartphone camera lenses, made its debut at COMPUTEX this year, exhibiting jointly with Ability Opto-Electronics Technology (AOET), of which Largan is the largest shareholder with approximately 15.2% stake. Leveraging its deep expertise in micro-optics design, Largan has developed its own optical coupling technology and unveiled first-ever samples of a multi-channel Photonic Module Lens Assembly (PMLA) and a 2D Fiber Array Unit (FAU).

The PMLA is an integrated optical component combining a prism and collimating lens to redirect the optical path and improve coupling precision. The 2D FAU uses stacked fiber routing to increase fiber density and improve alignment tolerance. The FAU sample demonstrated at the show supports 40 channels across four stacked layers, with 10 channels per layer.

Also worth noting: AOET displayed Metalens technology applicable to IR cameras and sensors, and announced plans to leverage its micro-glass processing capabilities to enter the FAU V-groove foundry segment.

AuthenX - FAU

AuthenX, a subsidiary of EZconn, showcased a Detachable 2D FAU and its application on a CPO chip. AuthenX’s Detachable 2D FAU (40-lens) is distinguished by its proprietary Metalens technology and optical coupling design, combined with a detachable architecture that simplifies maintenance and reduces the time required for repeated optical coupling operations.

LINTES – CPO/CPC Socket

LINTES, a subsidiary of LOTES, demonstrated a universal CPO/CPC socket and provided a live demonstration of CPC applications on-site. The socket is designed by LINTES and tooled for mass production by LOTES.

The CPO/CPC universal socket accommodates 12 Presslink Ultra CPC plugs. Each copper wire on the Presslink Ultra delivers 200 Gbps, with a single plug reaching an aggregate bandwidth of 3.2 Tbps. At this data rate, CPC transmission distance can reliably reach approximately 0.5 meters.

LINTES also displayed an optical engine set sample, an 800G LPO AOC sample, and an 800G OSFP Transceiver sample.

SK hynix - HBF & HBM & BlueField-4 STX

SK hynix presented a full product lineup covering the memory hierarchy for KV cache offloading (KV cache offloading will be explored in depth in our future article). At the G1 (GPU) tier, SK hynix displayed a schematic of its latest AI-N B (Bandwidth) product, which vertically stacks NAND to simultaneously achieve high memory capacity and bandwidth - also known as HBF (High Bandwidth Flash). In addition, SK hynix exhibited physical samples of each HBM generation from HBM2E through HBM4E.

Related report: Crossing AI Memory Wall: Storage Layer Reallocation and HBF Analysis

At the G2 (System Memory) tier, SK hynix showcased its LPDDR5X and DDR5 product lines. At the G3 (Local Storage) through G4 (Network Storage) tiers, the company also exhibited its SSD product line.

Notably, targeting NVIDIA’s newly added G3.5 (Context Memory Storage) tier, SK hynix displayed the PE9010 M.2 and PEB210 E1.S SSDs designed for use in BlueField-4 STX.

Samsung Semiconductor - HPB & HBM5

Samsung Semiconductor debuted a physical mockup of its next-generation HBM5. Of particular note, Samsung is set to adopt its proprietary HPB (Heat Path Block) thermal architecture in HBM5 for the first time, designed to address heat buildup in the Base Die under high-bandwidth operation.

The key design highlight of HPB is the addition of a separate chimney-like thermal structure directly on the D2D PHY responsible for HBM-to-GPU data transfer, allowing heat to be conducted out directly, thereby reducing thermal resistance and improving operational stability. Similarly, SK hynix’s previously announced iHBM platform plans to stack ICE (Integrated Cooling Elements) directly on the D2D PHY, which is expected to reduce thermal resistance by more than 30%. These designs are expected to indirectly drive an increase in HBM Base Die area in future generations.

Related report: 2Q26 HBM Market Dynamics and Forecast

Samsung Semiconductor also exhibited physical Core Die and Base Die samples for HBM4E and next-generation HBM (HBM5). Notably, the HBM4E Base Die uses Samsung’s 4nm process, while the HBM5 Base Die is expected to make a generational leap to Samsung’s 2nm process.

In addition, the company showcased its AI memory portfolio across the KV cache memory hierarchy, including the HBM4 at the G1 (GPU) tier, LPDDR5X at the G2 (System Memory) tier, PM1763 SSD at the G3 (Local Storage) tier, PM1753 SSD at the G3.5 (Context Memory Storage) tier, and PM9D3a SSD at the G4 (Network Storage) tier - going head-to-head with SK hynix.

HANMI Semiconductor - HBM Fluxless TC Bonder

HANMI Semiconductor, the leading manufacturer of HBM TC Bonders, exhibited its Wide TC Bonder designed specifically for next-generation HBM (HBM5 and HBM6). In addition to supporting larger die areas, the Wide TC Bonder can be optionally configured with a Fluxless version to improve bonding accuracy, filling the gap between conventional TC Bonders and Hybrid Bonders.

PSMC - WoW (Wafer-on-Wafer)

Taiwan-based memory manufacturer PSMC (Powerchip Semiconductor Manufacturing Corporation) presented under the theme “3D AI Foundry,” collaborating with partners including AP Memory, Syntronix, ESMT, and A.I. Memory to build a fully integrated ecosystem spanning IP, IC design, foundry, OSAT, and end applications. One of the highlights was its WoW (Wafer-on-Wafer) 3D stacking technology.

Unlike ESMT’s aiPIM, which focuses on vertically stacking DRAM dies on top of a larger Logic Die, WoW technology stacks an entire Memory wafer on top of an entire Logic wafer, improving bonding efficiency.

PSMC’s group partner A.I. Memory, an IC design company focused on AI-in-Memory technology, showcased AIM 3.0, its first product to adopt Hybrid Bonding. Due to its vertical stacking design, the chip footprint is compact, making it well-suited for small Edge AI devices such as IP cameras, where real-time facial recognition is supported.

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From Nvidia’s multi-billion dollar bet and the wave of startup launches to capital markets beginning to price these companies, it is clear that in the AI inference era, industry competition has shifted from building “bigger” models to “more efficient” models. This article will explore:

• The trend of AI shifting from training toward inference

• Architectural bottlenecks of general-purpose GPUs

• Advantages and challenges of hard-coded inference chips

• An overview of high-efficiency inference chip startups

Related report: NVIDIA FY1Q27 AI Server Outlook: GB/VR Rack Leads

Industry Shift: From Training to Inference

In the early days of generative AI’s rise in 2022, industry competition focused on model training. Whoever could train the most powerful model held the competitive edge, leading companies to pour massive capital into stacking parameters and chip resources in pursuit of leaps in model scale and capability.

However, as AI services enter routine deployment, the cost structure has changed. Unlike training, which is a high-capital but low-frequency R&D expense, inference is a high-frequency, long-term cost directly tied to revenue. Cost per token and energy efficiency directly affect gross margins and the ability to scale. Every API call and every generated token represents compute consumption and margin pressure. If token generation costs cannot decline with scale, the sustainability of the business model comes into question.

Consequently, the focus of hardware and software development has shifted toward throughput, energy efficiency, and memory architecture optimization, emphasizing data movement efficiency and low-latency design rather than simply pursuing peak compute performance.

Related report: NA CSPs Capex Surge Powers AI Infra Expansion

Architectural Bottlenecks of General-Purpose GPUs

Traditional general-purpose GPUs rely on HBM and external DRAM to store model weights, with compute cores physically separated from memory. Data must frequently move between the chip and the package. As inference traffic grows continuously, the architectural bottleneck of general-purpose GPUs becomes increasingly apparent.

For Transformer inference based on matrix multiplication, memory bandwidth and access latency are the primary constraints. While HBM provides high bandwidth, it comes with complex packaging, yield issues and high costs, and rising power consumption as bandwidth scales. For low-batch, low-latency requests, GPUs struggle to leverage their massive parallel advantage, leading to decreased utilization and higher costs per token.

On the other hand, as model scale is no longer the sole measure of competitiveness, the market has begun exploring ways to compress models while preserving inference capability. For example, 1.58-bit quantization and weight pruning enable models to maintain inference accuracy at extremely low memory footprints; Mixture-of-Experts (MoE) architectures reduce actual computation through a “partial activation” mechanism that activates only a small subset of expert sub-networks during each inference pass.

The rise of lean models opens a new direction for hardware design: when model weights and structure become stable and no longer require expensive dynamic memory to support flexibility, the path of embedding algorithms directly into silicon becomes commercially viable.

Related report: Crossing AI Memory Wall: Storage Layer Reallocation and HBF Analysis

Hard-coded Inference Chips: Advantages in Power, Cooling, and Capital Efficiency

Hard-coded inference chips emerged in response to efficiency bottlenecks. Vendors such as Taalas embed model weights in Mask ROM (Read-Only Memory) and use on-chip SRAM to handle dynamic data, drastically reducing the power consumed by external memory data movement and significantly improving tokens per watt and tokens per dollar. The primary benefits are low latency, low power consumption, and high throughput, with simplified cooling and packaging design.

However, the market’s primary concern remains hardware inflexibility in the face of rapidly evolving model updates. As a structural risk, specialized chips offer little room for adjustment compared to programmable architectures. Use cases must be highly stable and deployment scales sufficiently large to amortize non-recurring engineering (NRE) costs. The ecosystem also presents a meaningful barrier: cloud markets continue to rely on general-purpose platforms, and customers may prefer flexible solutions that can evolve alongside model upgrades.

To mitigate these risks, vendors are pursuing automated model-to-chip pipelines, pre-fabricated wafers, and hybrid programmable architectures integrating quantization and LoRA fine-tuning, striking a balance between hard-wiring and flexibility to enable commercial deployment.

Going forward, hard-coded technology is expected to gain traction in ultra-low-latency applications and closed-deployment scenarios where model structures are stable, privacy requirements are high, and deployment scales are well-defined. Hard-coded chips can operate in standard air-cooled racks, reducing energy consumption and capital expenditures, making them particularly attractive to cloud service providers and vertical integrators. Conversely, traditional ASIC vendors relying on software-compiled scheduling will face performance pressure at the architecture level.

Overall, TrendForce expects general-purpose GPUs to continue dominating training and multi-model environments. In mature, predictable inference scenarios, specialized architectures are expected to carve out their own space, not by displacing GPUs, but by addressing use cases where efficiency and cost structure matter most. The industry is thus evolving toward a dual-track structure where general-purpose and specialized computing coexist.

Taalas HC1: Proof of Concept for Hard-coded Inference

On February 20, 2026, Canadian AI chip startup Taalas launched the Taalas HC1, hard-wiring Llama 3.1 8B model directly into the chip, achieving a throughput of 16,960 tokens/s/user.

Moreover, the Taalas HC1 uses TSMC’s N6 process, requires no HBM memory or CoWoS packaging, and has a single-chip TDP of approximately 250W (air-cooled). Based on Taalas's analysis, compared to the Nvidia B200 (throughput optimized) running Llama 3.1 8B at a cost of 3.79 cents per million tokens, the Taalas HC1 achieves a cost of just 0.75 cents per million tokens, approximately one-fifth.

The key to Taalas’s compute efficiency lies in adopting the concept of Computing-in-Memory (CIM). CIM integrates compute functions within memory to perform computation directly within memory, eliminating the need for frequent data transfers between compute units and memory, thus removing the memory wall bottleneck, and reducing excess latency and power consumption during computation.

What is Computing-in-Memory? Since mathematician John von Neumann published the von Neumann architecture in 1945, chip design has followed a structure where components such as the Central Arithmetical (CA) unit and the Memory (M) unit are separate to maintain greater flexibility.

However, as the growth of memory bandwidth and computing power has become increasingly mismatched, the transfer of data between the computing unit and memory has become a major constraint. Computing-in-Memory (CIM) emerged to address this, evolving into various forms such as Digital CIM (DCIM), Analog CIM (ACIM), and Hybrid CIM. Nevertheless, the programming languages, underlying software architectures, and applications capable of running on CIM are not yet fully developed, and the technology remains in its early stages of development.

Compared to conventional CIM implementations, Taalas takes a more radical approach through hard-coding. Operating on the philosophy that “The Model is The Computer,” Taalas creates a fully hardware-defined AI hardcore model that embeds model weights directly into the chip’s Mask ROM. This captures the low-latency and low-power benefits of CIM while bypassing the bottleneck of CIM’s currently immature software ecosystem.

Beyond exceptional compute efficiency, by using high-density ROM to store model weights, Taalas can produce a dedicated chip for a new AI model by modifying just 2 mask layers — converting an AI model into a physical chip in just 2 months. Taalas also retains a portion of SRAM for KV cache and LoRA fine-tuning weights, compensating for the lack of flexibility.

Despite their different implementations, Taalas’s fully hardware-defined approach and Groq’s fully software-defined approach share the same goal: to achieve static scheduling and fully deterministic computation as much as possible, trading dynamic flexibility for maximum efficiency.

A New Era of Inference Chips: Diverse Technology Paths in Parallel

Beyond Taalas, a growing number of AI chip startups specializing in high-efficiency inference have entered the space, including Tenstorrent, Groq, Cerebras, SambaNova, MatX, Untether AI, Hepzibah AI, Etched, d-Matrix, Positron AI, Axelera AI, and FuriosaAI. Chip specifications across vendors are summarized below:

Implementation methods vary across Hard-Wired and CIM vendors. Taalas HC1 directly hard-wires model weights into Mask ROM (fully hardware-defined). Etched Sohu similarly uses a hard-wired architecture but applies to all Transformer models, offering greater flexibility. Within CIM: d-Matrix Corsair uses Digital Computing-in-Memory (DIMC) as its core technology, embedding the AI model’s underlying architecture into the chip, applicable to all AI models with even greater flexibility than Etched. Untether AI Boqueria uses at-memory compute, integrating RISC-V processors and processing elements directly within SRAM memory banks. Axelera AI Europa AIPU also uses Digital In-Memory Computing (D-IMC), with RISC-V controlling the data flow.

On May 14, 2026, Cerebras, currently the most talked-about name in the inference chip space, officially listed on the Nasdaq. Its core technology is Wafer-Scale Integration (WSI), which consolidates an entire 12-inch wafer into a single chip (WSE-3), delivering 44GB of on-chip SRAM and 21 PB/s of bandwidth. Cerebras has also secured a three-year compute partnership with OpenAI valued at over $20 billion and 750MW in capacity.

Currently, the market is in an early exploratory phase with multiple parallel tracks. Startups are simultaneously pursuing different technology paths, including Computing-in-Memory (CIM), SRAM-first architectures, wafer-scale integration, and tensor contraction processor. It is expected that future inference chip architectures will gradually integrate these various approaches to meet the performance and efficiency demands of AI inference.

In 2026, as AI data centers face growing power bottlenecks and EVs accelerate the adoption of high-voltage architectures, SiC and GaN technologies are increasing their share across global infrastructure.

This article explores the deployment of these technologies across AI/data center infrastructure and automotive and industrial systems, while providing insights into the evolving competitive landscape of the global supply chain.

Related report: 2026 AI Factory Infrastructure Outlook: HVDC Power & Liquid Cooling Trends

SiC/GaN Are Entering a Structural Growth Cycle

Driven by the global push toward smart grids, rising energy efficiency standards in AI data centers, and the accelerating adoption of high-voltage EV platforms, power devices are no longer peripheral components—they have become strategic essentials reshaping the global energy landscape.

Leading players such as Infineon, STMicroelectronics, onsemi, and ROHM Semiconductor are deepening vertical integration across the supply chain, transforming into full-stack energy management solution providers. This marks the entry of power semiconductors into a structural growth cycle.

Meanwhile, China’s power semiconductor industry has moved beyond the technology validation phase and is rapidly expanding thanks to national infrastructure strategies.

In 2026, competition will no longer center solely on performance. Instead, it will increasingly hinge on control over critical materials (such as high-quality crystal growth techniques) and advanced packaging capabilities (including silver sintering and pressure bonding).

As leading compound semiconductor technologies, SiC and GaN are driving breakthroughs in crystal growth, epitaxy, and wafer processing. These advances are accelerating the transition from discrete components to integrated modules, meeting market demand for extreme miniaturization and superior thermal performance.

Driven by both AI/data center infrastructure and automotive and industrial systems as dual growth engines, the market penetration of third-gen semiconductors is expected to continue to rise in 2026.

Related report: 2026 Global SiC Power Device Market Analysis Report

SiC is vital to the front-end and mid-stage power conversion within data center architectures, managing the highest voltages and power loads. With superior thermal performance and switching characteristics, SiC is essential for the development of next-generation solid-state transformers (SSTs).

Discussions regarding SSTs have intensified recently. SSTs can directly convert medium-voltage AC from the grid into the 800V DC required for AI infrastructure. Built on power electronics and wide-bandgap (WBG) semiconductor technology, SSTs serve as an alternative to traditional 50/60Hz transformers. Beyond significantly reducing footprint and improving energy efficiency, they offer precise, real-time control over power flow, potentially reshaping the design of medium-voltage power conversion systems.

From an application perspective, SSTs are suited to any scenario requiring efficient medium-voltage AC-to-DC conversion, including AI data centers, renewable energy systems, and EV charging infrastructure—making them a key direction for the next generation of power electronics upgrades. Driven by the extreme demands for power efficiency and density within AI compute clusters, SSTs are rapidly becoming the core solution for power supply transformation in future AI data centers.

Meanwhile, GaN, known for its high-frequency and high-efficiency properties, is becoming increasingly popular in mid- and end-stage power conversion. It supports ultra-high-power density and quick dynamic responses. Typical applications include AI server power units, data center PSUs, telecom power systems, and high-efficiency fast-charging devices. As the rapid proliferation of AI drives up power consumption and density requirements, HVDC architectures and high-efficiency conversion designs are becoming the industry standard. GaN components effectively reduce conduction and switching losses, allowing for significantly smaller magnetic components and a reduced thermal footprint.

Despite its advantages, GaN is still limited in ultra-high-voltage applications and extreme power density scenarios, where it must complement other wide-bandgap materials such as SiC. Furthermore, long-term reliability and durability standards for GaN in certain high-power applications still require further validation and standardization.

SiC/GaN in AI/Data Center Infrastructure

AI development has shifted from cloud-based training to large-scale inference applications, driving upgrades across servers, racks, power systems, and supporting infrastructure such as electrical systems and precision cooling (CRAC/CRAH). Even as AI chip process nodes advance to 2 nm and beyond, scaling alone is no longer sufficient to close the compute gap. Meanwhile, expansion is increasingly constrained by a physical “power wall,” turning AI competition into a fundamentally energy-driven race.

At the front end of power delivery, traditional AC architectures rely on multiple voltage conversion stages, each introducing significant thermal losses. In contrast, SiC-enabled HVDC architectures support direct high-voltage DC transmission, simplifying the conversion chain and minimizing energy loss. This enables a more efficient “grid-to-rack” power structure, forming a resilient and high-efficiency energy backbone for data centers.

At the rack and server level, GaN-based solutions can push power conversion efficiency beyond 96% to meet the highest titanium-level standards for energy efficiency. This translates into lower electricity costs, while significantly improving thermal headroom and power density within servers.

Related report: 2026 AI Server Outlook: CSP Rack Power Scales Up

SiC/GaN in Automotive and Industrial Systems

Global automakers are continuing to adopt 800V high-voltage platforms, driving the expansion of SiC power module capacity and contributing to cost reductions. Across mobility applications, including electric buses and trucks, this high-efficiency architecture is becoming a strategic foundation for improving driving range and charging speed.

Related report: 1Q26 Global Automotive Market Decode

For example, Tesla and BYD are enhancing energy efficiency across core vehicle models by adopting SiC chips and developing key power electronics in-house. Meanwhile, Hyundai and Kia have integrated SiC into their E-GMP platform, achieving a 5% increase in driving range alongside ultra-fast charging capabilities. Even in hybrid systems, Toyota has introduced SiC into the motor controller of its sixth-generation THS to improve PCU (Power Control Unit) efficiency and reduce power loss.

Market trends indicate that SiC and GaN technologies are driving convergence between energy systems and transportation infrastructure. GaN, in particular, is expanding beyond consumer electronics into automotive applications such as on-board chargers (OBC), DC/DC converters, LiDAR systems, and infotainment/audio amplifiers.

Leading companies, including Infineon, STMicroelectronics, EPC, Texas Instruments (TI), and ROHM, have already introduced automotive-grade solutions. For instance, Infineon has begun mass production of its CoolGaN 100V G1 automotive transistors and launched AEC-Q101-qualified GaN components.

Additionally, Tata Electronics has partnered with ROHM to focus on assembly and testing of automotive MOSFET power devices, linking local manufacturing capabilities with the global supply chain. This highlights the expanding structural role of power semiconductors within automotive systems.

Overall, SiC has become the standard specification for main traction inverters in 800V platforms or vehicle models with a driving range of 700km+. Meanwhile, GaN is entering a mass adoption phase. Although its penetration in main traction systems remains lower than SiC, GaN is increasingly favored in on-board charging, lightweight power modules, and LiDAR applications, where it helps reduce vehicle weight and free up interior space.

For a full analysis of the competitive landscape, access our report: SiC/GaN Power Semiconductors Break “AI Power Wall,” Reshaping Data Center Power Supply.

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The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.

As AI and HPC workloads drive chip packages to ever-larger form factors, the area utilization limits of circular wafers are becoming an increasingly important consideration. Panel-Level Packaging (PLP) addresses this directly by moving to square panels, which deliver higher area utilization and better alignment with large-die form factors.

Major foundries and OSATs including TSMC, Intel, Samsung, Rapidus, and Amkor are all advancing their PLP roadmaps. TSMC, through its subsidiary VisEra, plans to establish a CoPoS pilot line with trial production targeted for 2027, positioning 2026 as a critical window for product validation and deliveries for related equipment and material providers.

The central technical challenge, however, is warpage. As panel size grows and layer counts increase, thermal stress from CTE mismatches between materials compounds in ways that directly affect yield. To address this issue, specialty chemical suppliers such as AMC, WaferChem, and Everlight Chemical showcased corresponding solutions at Touch Taiwan 2026 in April. This article focuses on two key material approaches, Low-Temperature Curable PSPI and Balance Film, and maps out the current supplier landscape.

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Related report: T-Glass Supply Shortages: AI Rack Fiberglass Trends

As AI chips grow more complex, package sizes keep expanding, and traditional organic substrates are reaching their limits. Under high temperatures during assembly, warpage reduces yield and becomes increasingly difficult to manage as package sizes grow.

Against this backdrop, glass, with better thermal and mechanical properties, is emerging as the next-generation material for advanced packaging. Glass-based solutions fall into two categories: one replaces the core layer of the substrate with glass, known as a glass core substrate; the other replaces the silicon interposer with glass, known as a glass interposer.

Intel has been an active mover in glass substrate technology. As early as 2023, Intel committed to glass substrates in its advanced packaging roadmap. In January 2026, it debuted the first sample combining EMIB packaging with a glass core substrate at NEPCON Japan — achieving No SeWaRe, or no micro-cracks — marking a decisive step toward commercial reality.

Meanwhile, Samsung and Rapidus are expected to roll out glass interposer solutions, while SK Absolics is targeting mass production of glass substrates in 2026.

This article covers the technical advantages of glass substrates, the manufacturing challenges that remain, and how the supplier landscape is taking shape.

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Correction: An earlier version of this article incorrectly listed the English name of glass fiber cloth supplier 宏和電子材料 as "Hongho Precision Textile." The correct English name is Grace Fabric Technology. We apologize for the error and have updated the text and charts accordingly.

The AI infrastructure buildout is often discussed in terms of chips and computing power. But beneath the surface, a set of supply chain bottlenecks is quietly shaping the pace and cost of deployment. Last week, we looked at CPO testing. This week: glass fiber cloth.

The arrival of the Nvidia Rubin generation is reshaping the demand structure for advanced substrate and PCB materials. Compared to its predecessor, the Rubin GPU substrate has seen significant increases in both area and layer count. Furthermore, cableless designs have catalyzed new demand for midplanes and orthogonal backplanes. The introduction of the Rubin LPX rack, a disaggregated rack for inference, has further expanded the overall consumption of high-end glass fiber cloth.

Related report: 2026 Outlook: NVIDIA Rubin Drives New Wave of AI Hardware Upgrades

On the supply side, however, the market faces severe constraints. Nittobo, the leading manufacturer holding approximately 90% market share in T-glass and 60-70% in NER-glass, is not expected to bring new capacity online until mid-2027 at the earliest. Consequently, critical material gaps cannot be filled in the short term. Glass fiber cloth has transitioned from a rarely discussed “supporting role” to a critical bottleneck affecting the lead times and costs of the entire AI server supply chain.

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Here’s what they said, and what it means for the structural shift in CPU:GPU ratios that we’ve been tracking.

Intel: The Ratio Is Already Shifting

During Intel’s Q1 2026 earnings call on April 23, CEO Lip-Bu Tan put a number on the shift:

The feedback from customers is that CPU is very important when they move from training to inference. The inference side — in terms of orchestration, control plane, and also managing all the different agents with data — CPU is much more efficient. The ratio of CPU to GPUs used to be 1 to 8, and now it’s 1 to 4, and I think towards parity or even better. The demand is very strong.

CFO David Zinsner mapped out the full range on the same call: training runs at roughly 7–8 GPUs per CPU; inference compresses that to 3–4:1; and for agentic and multi-agent workloads, the ratio could compress further, potentially even flipping in favor of CPUs.

Google: “General-Purpose Compute Is Going to Make a Comeback”

At Google Cloud Next 2026, Amin Vahdat, Google SVP and Chief Technologist for AI and Infrastructure, made a notable prediction about CPUs:

CPU will come back. Running these agents involves a lot of general-purpose compute — they’re orchestrating all the inference that’s going on. They create sandboxes, virtual machines to build code, run it, check the results, and then figure out the next set of outputs. So general-purpose compute is going to make a comeback.

The framing matters: this is not CPU replacing specialized accelerators, but CPU orchestrating them. Vahdat also noted that the age of purpose-built accelerators isn’t going away — specialization, he said, is going to continue.

TSMC: CPUs Are “More and More Important”

On April 16, TSMC Chairman and CEO C.C. Wei highlighted a key demand driver during the Q1 2026 earnings call: the shift from Generative AI’s query mode to Agentic AI’s command-and-action mode is leading to another step-up in token consumption, sustaining demand for leading-edge silicon.

On CPUs, Wei acknowledged they are becoming “more and more important” in today’s AI data centers. However, CPUs remain excluded from TSMC’s AI revenue calculation for a practical reason: TSMC currently cannot distinguish whether a CPU is destined for a PC, a desktop, or an AI data center. Wei noted the company may reconsider the definition in the future.

For the full analysis, see TrendForce's recent report, where we cover the competitive landscape across Intel, AMD, Nvidia, Arm, and the major CSPs, plus our projections on supply constraints and IC back-end design service opportunities.

2026 Agentic AI Wave: CPU Shortage and GPU Ratio Structural Changes