In 2026, as AI data centers face growing power bottlenecks and EVs accelerate the adoption of high-voltage architectures, SiC and GaN technologies are increasing their share across global infrastructure.

This article explores the deployment of these technologies across AI/data center infrastructure and automotive and industrial systems, while providing insights into the evolving competitive landscape of the global supply chain.

Related report: 2026 AI Factory Infrastructure Outlook: HVDC Power & Liquid Cooling Trends

SiC/GaN Are Entering a Structural Growth Cycle

Driven by the global push toward smart grids, rising energy efficiency standards in AI data centers, and the accelerating adoption of high-voltage EV platforms, power devices are no longer peripheral components—they have become strategic essentials reshaping the global energy landscape.

Leading players such as Infineon, STMicroelectronics, onsemi, and ROHM Semiconductor are deepening vertical integration across the supply chain, transforming into full-stack energy management solution providers. This marks the entry of power semiconductors into a structural growth cycle.

Meanwhile, China’s power semiconductor industry has moved beyond the technology validation phase and is rapidly expanding thanks to national infrastructure strategies.

In 2026, competition will no longer center solely on performance. Instead, it will increasingly hinge on control over critical materials (such as high-quality crystal growth techniques) and advanced packaging capabilities (including silver sintering and pressure bonding).

As leading compound semiconductor technologies, SiC and GaN are driving breakthroughs in crystal growth, epitaxy, and wafer processing. These advances are accelerating the transition from discrete components to integrated modules, meeting market demand for extreme miniaturization and superior thermal performance.

Driven by both AI/data center infrastructure and automotive and industrial systems as dual growth engines, the market penetration of third-gen semiconductors is expected to continue to rise in 2026.

Related report: 2026 Global SiC Power Device Market Analysis Report

SiC is vital to the front-end and mid-stage power conversion within data center architectures, managing the highest voltages and power loads. With superior thermal performance and switching characteristics, SiC is essential for the development of next-generation solid-state transformers (SSTs).

Discussions regarding SSTs have intensified recently. SSTs can directly convert medium-voltage AC from the grid into the 800V DC required for AI infrastructure. Built on power electronics and wide-bandgap (WBG) semiconductor technology, SSTs serve as an alternative to traditional 50/60Hz transformers. Beyond significantly reducing footprint and improving energy efficiency, they offer precise, real-time control over power flow, potentially reshaping the design of medium-voltage power conversion systems.

From an application perspective, SSTs are suited to any scenario requiring efficient medium-voltage AC-to-DC conversion, including AI data centers, renewable energy systems, and EV charging infrastructure—making them a key direction for the next generation of power electronics upgrades. Driven by the extreme demands for power efficiency and density within AI compute clusters, SSTs are rapidly becoming the core solution for power supply transformation in future AI data centers.

Meanwhile, GaN, known for its high-frequency and high-efficiency properties, is becoming increasingly popular in mid- and end-stage power conversion. It supports ultra-high-power density and quick dynamic responses. Typical applications include AI server power units, data center PSUs, telecom power systems, and high-efficiency fast-charging devices. As the rapid proliferation of AI drives up power consumption and density requirements, HVDC architectures and high-efficiency conversion designs are becoming the industry standard. GaN components effectively reduce conduction and switching losses, allowing for significantly smaller magnetic components and a reduced thermal footprint.

Despite its advantages, GaN is still limited in ultra-high-voltage applications and extreme power density scenarios, where it must complement other wide-bandgap materials such as SiC. Furthermore, long-term reliability and durability standards for GaN in certain high-power applications still require further validation and standardization.

SiC/GaN in AI/Data Center Infrastructure

AI development has shifted from cloud-based training to large-scale inference applications, driving upgrades across servers, racks, power systems, and supporting infrastructure such as electrical systems and precision cooling (CRAC/CRAH). Even as AI chip process nodes advance to 2 nm and beyond, scaling alone is no longer sufficient to close the compute gap. Meanwhile, expansion is increasingly constrained by a physical “power wall,” turning AI competition into a fundamentally energy-driven race.

At the front end of power delivery, traditional AC architectures rely on multiple voltage conversion stages, each introducing significant thermal losses. In contrast, SiC-enabled HVDC architectures support direct high-voltage DC transmission, simplifying the conversion chain and minimizing energy loss. This enables a more efficient “grid-to-rack” power structure, forming a resilient and high-efficiency energy backbone for data centers.

At the rack and server level, GaN-based solutions can push power conversion efficiency beyond 96% to meet the highest titanium-level standards for energy efficiency. This translates into lower electricity costs, while significantly improving thermal headroom and power density within servers.

Related report: 2026 AI Server Outlook: CSP Rack Power Scales Up

SiC/GaN in Automotive and Industrial Systems

Global automakers are continuing to adopt 800V high-voltage platforms, driving the expansion of SiC power module capacity and contributing to cost reductions. Across mobility applications, including electric buses and trucks, this high-efficiency architecture is becoming a strategic foundation for improving driving range and charging speed.

Related report: 1Q26 Global Automotive Market Decode

For example, Tesla and BYD are enhancing energy efficiency across core vehicle models by adopting SiC chips and developing key power electronics in-house. Meanwhile, Hyundai and Kia have integrated SiC into their E-GMP platform, achieving a 5% increase in driving range alongside ultra-fast charging capabilities. Even in hybrid systems, Toyota has introduced SiC into the motor controller of its sixth-generation THS to improve PCU (Power Control Unit) efficiency and reduce power loss.

Market trends indicate that SiC and GaN technologies are driving convergence between energy systems and transportation infrastructure. GaN, in particular, is expanding beyond consumer electronics into automotive applications such as on-board chargers (OBC), DC/DC converters, LiDAR systems, and infotainment/audio amplifiers.

Leading companies, including Infineon, STMicroelectronics, EPC, Texas Instruments (TI), and ROHM, have already introduced automotive-grade solutions. For instance, Infineon has begun mass production of its CoolGaN 100V G1 automotive transistors and launched AEC-Q101-qualified GaN components.

Additionally, Tata Electronics has partnered with ROHM to focus on assembly and testing of automotive MOSFET power devices, linking local manufacturing capabilities with the global supply chain. This highlights the expanding structural role of power semiconductors within automotive systems.

Overall, SiC has become the standard specification for main traction inverters in 800V platforms or vehicle models with a driving range of 700km+. Meanwhile, GaN is entering a mass adoption phase. Although its penetration in main traction systems remains lower than SiC, GaN is increasingly favored in on-board charging, lightweight power modules, and LiDAR applications, where it helps reduce vehicle weight and free up interior space.

For a full analysis of the competitive landscape, access our report: SiC/GaN Power Semiconductors Break “AI Power Wall,” Reshaping Data Center Power Supply.

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The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.

As AI and HPC workloads drive chip packages to ever-larger form factors, the area utilization limits of circular wafers are becoming an increasingly important consideration. Panel-Level Packaging (PLP) addresses this directly by moving to square panels, which deliver higher area utilization and better alignment with large-die form factors.

Major foundries and OSATs including TSMC, Intel, Samsung, Rapidus, and Amkor are all advancing their PLP roadmaps. TSMC, through its subsidiary VisEra, plans to establish a CoPoS pilot line with trial production targeted for 2027, positioning 2026 as a critical window for product validation and deliveries for related equipment and material providers.

The central technical challenge, however, is warpage. As panel size grows and layer counts increase, thermal stress from CTE mismatches between materials compounds in ways that directly affect yield. To address this issue, specialty chemical suppliers such as AMC, WaferChem, and Everlight Chemical showcased corresponding solutions at Touch Taiwan 2026 in April. This article focuses on two key material approaches, Low-Temperature Curable PSPI and Balance Film, and maps out the current supplier landscape.

From Round to Square: The Rise of PLP

As AI model parameters grow exponentially, demand for computing performance continues to rise. With semiconductor process scaling approaching its physical limits, the industry has turned to assembling and stacking multiple chiplets on a single interposer to boost performance, driving a steady increase in package size. TSMC expects to achieve a 9.5x reticle size with its CoWoS-L packaging by 2027, while Intel plans to reach a 12x reticle size with its EMIB packaging by 2028.

Related report: Global AI Server & Supply Chain Outlook 2026

However, the continuous expansion of package sizes presents two major challenges: (1) the inefficiency of fitting square chips onto the edges of circular wafers, which reduces the area utilization rate for large-size packages; and (2) increasingly severe warpage issues, where warped sections of the substrate lead to poor contact.

To overcome these limitations, panel-level packaging (PLP) has come to the forefront. By transitioning from circular wafers to square or rectangular panels, chip edges can align seamlessly with the panel edges, thereby improving area utilization.

Currently, foundries, OSATs, material suppliers, and traditional LCD panel makers are all actively developing PLP technology. Mass production has been reached for relatively mature processes, such as the ones used to manufacture RF chips and PMICs (with an RDL L/S of approximately 10-20 μm). Conversely, advanced PLP processes for AI chips (with an RDL L/S of approximately 1-10 μm) have not yet entered mass production. Meanwhile, the industry is actively exploring both material and equipment solutions to address the warpage challenge.

What Causes Warpage and How to Fix It

The main cause of warpage is CTE mismatch between different materials, which generates stress differences during temperature changes and leads to bending. The magnitude of warpage is measured as the vertical distance between the highest and lowest points of the deformed surface, known as the peak-to-valley distance.

This problem increases non‑linearly with factors such as (1) larger panel area, (2) greater variety of materials, (3) larger CTE gaps between materials, (4) thinner thickness, and (5) more RDL layers. Whether the deformation appears as a concave ( “smiling face”) or convex (“frowning face”) profile, the result is poor contact between the chiplet and the panel.

Notably, the “chip-first” and “chip-last” processes in advanced packaging involve different warpage mechanisms, with variations in both timing and severity.

(1) Chip First：

The chip-first process comes in two variants: face-up and face-down. In the face-up approach, chips are mounted onto a glass carrier and encapsulated. The epoxy molding compound (EMC) is then ground down to expose the chip before the RDL is fabricated. In the face-down approach, the glass carrier is removed immediately after chip encapsulation, and the RDL is fabricated on the underside.

(2) Chip Last：

In the chip-last process, the RDL is fabricated on a glass carrier first, and the chip is mounted and encapsulated afterward. Because encapsulation occurs after RDL fabrication, the accumulated thermal stress is comparatively lower, making the assembly less prone to severe warpage. Furthermore, since chip placement occurs at a later stage, known good dies (KGDs) can be pre-screened and selectively placed, thereby improving overall packaging yields. Consequently, the chip-last process is predominantly utilized for high-end chip manufacturing, such as in TSMC’s CoWoS platform.

Materials and equipment providers have developed several solutions to address warpage. On the materials front, using a glass substrate as an interposer can resolve warpage at its source, as the CTE of glass (approximately 2.6 ppm/°C) closely matches that of silicon. However, glass is prone to micro-cracking (a.k.a. “SeWaRe”) during processing, and the supporting supply chain ecosystem is still developing.

Related report: Intel’s No SeWaRe Glass Substrates: TGV Challenges and Advanced Packaging Supply Chain Role

Alternatively, adopting low-temperature curable photosensitive polyimide (PSPI) as the interposer material can reduce processing temperatures and thereby mitigate warpage. However, it remains a significant R&D challenge to formulate a material that simultaneously offers low-temperature curability, a low CTE, a low dielectric constant (Dk), and high rigidity.

Another materials-based approach involves applying an anti-warpage balance film during processing to neutralize stress differentials. This resolves the warpage issue without modifying the core packaging materials. However, AMC is the sole supplier of high-end balance films at the present.

On the equipment front, thermocompression and vacuum suction can suppress deformation at the surface level, while selective laser modification alters the localized molecular structure within the material to relieve stress. However, surface-level suppression carries the risk of elastic rebound caused by residual stress once the panel leaves the equipment station, while selective laser modification remains largely in the R&D phase.

Material Solutions for Warpage Control

Low-Temperature Curable PSPI

Low-temperature curable PSPI reduces thermal stress accumulation by curing at below 250°C, significantly lower than the 300–350°C required for conventional PSPI. However, developing PSPI that simultaneously offers low CTE, low Dk, and high rigidity remains a significant R&D challenge. Conventional PSPI typically has a CTE of 40–80 ppm/°C and a Dk in the 2.8–3.6 range, far from the properties of glass.

Currently, most low‑temperature curable PSPI suppliers are Japanese companies such as Toray and FujiFilm. As the semiconductor industry shifts toward localized sourcing, Taiwan-based vendors are actively developing competing products, though achieving low CTE, low Dk, and sufficient tensile strength remains a challenge.

Balance Film

Balance film is formed by coating a base film with a special adhesive. When laminated onto a glass carrier or EMC, it generates a compensating stress in the opposite direction to offset thermal stress accumulated during processing.

The usage timing of balance film in a Chip Last process is as follows:

1. The RDL is first built on the glass carrier. A laser release layer is coated on the carrier to facilitate later separation, with no warpage at this stage.

2. A layer of balance film is pre‑laminated on the underside of the glass carrier to introduce warpage into the glass carrier as pre‑compensation.

3. As the RDL is built up layer by layer, the pre‑compensated panel is gradually pulled flat by the stress of the RDL layers; the balance film is replaced as needed until both the chips and EMC are completed, at which point there should be no warpage.

4. A layer of balance film is pre‑laminated on top of the EMC before de‑bonding the glass carrier, to avoid severe warpage that would occur if the glass carrier were removed directly.

5. After ball drop, dicing is performed; once the panel stress is released by dicing, the balance film is then removed.

A complete process thus requires at least two balance films (laminated on the glass carrier and the EMC respectively), with additional films added as RDL layer count increases.

If an optical engine (OE) is incorporated into the package, balance film can first be applied on top of the PIC to compensate for its larger warpage, followed by bonding the PIC to the substrate and then the EIC.

Warpage control has become a defining challenge as PLP scales toward advanced AI chip packaging. For a full analysis on the supplier landscape, access our report: Deconstructing PLP Warpage: Low-Temp PSPI, Balance Films, and Supplier Analysis.

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The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.

Related report: T-Glass Supply Shortages: AI Rack Fiberglass Trends

As AI chips grow more complex, package sizes keep expanding, and traditional organic substrates are reaching their limits. Under high temperatures during assembly, warpage reduces yield and becomes increasingly difficult to manage as package sizes grow.

Against this backdrop, glass, with better thermal and mechanical properties, is emerging as the next-generation material for advanced packaging. Glass-based solutions fall into two categories: one replaces the core layer of the substrate with glass, known as a glass core substrate; the other replaces the silicon interposer with glass, known as a glass interposer.

Intel has been an active mover in glass substrate technology. As early as 2023, Intel committed to glass substrates in its advanced packaging roadmap. In January 2026, it debuted the first sample combining EMIB packaging with a glass core substrate at NEPCON Japan — achieving No SeWaRe, or no micro-cracks — marking a decisive step toward commercial reality.

Meanwhile, TSMC, Samsung, and Rapidus are expected to roll out glass interposer solutions, while SK Absolics is targeting mass production of glass substrates in 2026.

This article covers the technical advantages of glass substrates, the manufacturing challenges that remain, and how the supplier landscape is taking shape.

Bigger Chips, Bigger Packaging Problems

As AI computing power requirements increase, the size of a single AI chip package is gradually expanding. Although ASML’s EUV (0.33 NA) currently limits the maximum reticle size to 26×33 mm (approximately 830 mm²), TSMC uses mask stitching technology to join multiple reticle patterns together in order to increase chip size.

Related report: Global AI Server & Supply Chain Outlook 2026

The single‑package size of NVIDIA’s Blackwell GPU is about 3.3× reticle size, roughly 2,739 mm². The next‑generation Rubin GPU is expected to expand to 4× reticle size, about 3,320 mm², while the Rubin Ultra GPU will reach 9× reticle size, about 7,470 mm². In addition to NVIDIA, Google’s TPU v9x (HumuFish) is also expected to adopt a large size of 9.5× reticle size.

According to TSMC’s CoWoS reticle size roadmap, the 5.5× reticle size variant is currently in mass production, with 9.5× targeted for 2027, 14× for 2028, and beyond 14× planned for 2029. Intel, meanwhile, is targeting a 12× reticle size EMIB solution by 2028 to address the demand for larger chip packages.

But scaling up package size introduces two key challenges.

First, square chips are increasingly hard to fit efficiently onto round wafers, which increases wasted area at the wafer edges. This led to the concept of panel‑level packaging (PLP), which uses square panels instead of round wafers, and is able to raise area utilization to over 75%.

Second, if large packages continue to use organic core substrate (mostly ABF materials made by laminating resin, glass fiber cloth, and copper foil), warpage during the reflow heating process becomes more severe, thereby reducing overall integration yield. (A deeper analysis of warpage challenges will be covered in our next article.)

Therefore, glass, which is flat in surface and is close to that of silicon (Si) in coefficient of thermal expansion (CTE), has become an ideal replacement for organic materials as an interposer or substrate.

Why Glass Substrates Outperform Organic Substrates

Simply put, better thermal, electrical, and physical properties.

• CTE close to silicon: Organic core substrates (OCS) have a CTE of roughly 7 ppm/°C, a significant mismatch with silicon’s 2.6 ppm/°C that could easily cause warpage. Glass, with a CTE of 3-9 ppm/°C, can be matched to silicon, maintaining stable yield even in large-size packages.

• Excellent dielectric performance: Glass is an excellent insulator. At 10 GHz, its dielectric constant (Dk) can be as low as 2.5-6, and its dielectric loss (Df) can be as low as 0.0005-0.005, allowing it to maintain signal integrity even in high‑speed transmission applications.

• Flat and smooth surface: Glass has extremely high surface flatness and smoothness, allowing it to achieve finer line width/spacing (L/S), such as <2 µm.

  

Who Is Building What, and When

As glass materials have excellent properties for advanced packaging, major foundries and OSATs are adding new product lines that use glass as either substrates or interposers.

TSMC unveiled its 310×310 mm CoPoS (Chip-on-Panel-on-Substrate) product line in 2025, and plans to establish a first mini production line at VisEra in 2026, begin small‑volume trial production in 2027, and reach mass production between 2028 and 2029. TSMC uses glass as an interposer in CoPoS, which requires a thinner profile (approximately 400 µm, roughly half the thickness of a substrate) and stricter CTE requirements, making it technically more challenging than glass used as a substrate.

Samsung announced at CES 2024 that it is developing glass interposer technology. In 2025, it established its first mini production line through SEMCO for glass core substrates, with mass production scheduled for 2027. Rapidus, meanwhile, showcased the largest glass interposer sample to date — measuring 600×600 mm — at SEMICON Japan 2025, with mass production targeted for 2028.

SK Group’s Absolics, a joint venture with Applied Materials, had already invested about KRW 300 billion in 2022 to build the first glass‑substrate factory in Covington, Georgia. Its goal is to develop glass substrates that can directly embed active/passive components, eliminating the interposer to reduce package area, thickness, and power consumption. The substrate measures 510×515 mm, with mass production planned for 2026.

Intel has been particularly active in glass substrate development. In September 2023, at Innovation Day, it announced plans to use glass substrates for advanced packaging, with mass production targeted between 2026 and 2030. On January 22, 2026, at NEPCON Japan, Intel showcased its first sample combining EMIB packaging with a glass core substrate. The package measures 78×77 mm (approximately 1,716 mm²), supports 2× reticle size, and uses a 10-2-10 stack structure (10 RDLs + 2 glass core layers + 10 RDLs, 22 layers total), with a total thickness of 800 µm and a bump pitch of 45 µm. Intel also reported achieving “No SeWaRe” (no micro-cracks) in testing, marking a decisive step toward mass production.

One Big Hurdle in Mass Production: SeWaRe

The biggest mass‑production challenge for glass substrates is “SeWaRe.” SeWaRe comes from the Japanese term 背割れ, meaning “back crack,” and refers to micro‑cracks that form during processing, especially drilling and dicing. As glass is brittle, micro‑cracks, once they appear, become stress‑concentration points that can cause the glass substrate to break during later testing and packaging steps.

As illustrated below, SeWaRe caused by dicing easily leads to near mode I fracture failure, which refers to the phenomenon where a material, under normal (perpendicular) stress, splits into upper and lower halves and fractures.

To reduce the probability of SeWaRe occurrence, the current mainstream glass substrate fabrication process includes:

1. Through-Glass Via, TGV: Typically, laser modification is first performed inside the glass, and then selective wet etching is applied to the modified regions to form TGV. TGV are X-shaped, because tapered sidewalls are better at distributing stress.

2. Polymer Lamination: A resin buffer layer is laminated onto the glass surface. Since copper (Cu) has a relatively high CTE, about 17 ppm/°C, the resin buffer layer prevents direct contact between the copper and the glass, avoiding cracking during thermal expansion and contraction.

3. Seed Sputtering: A metal seed layer is sputtered onto the surface.

4. Plating: A conformal metal layer is electroplated on the surface of the seed layer to reduce the amount of copper, and thereby prevent cracking during thermal expansion and contraction.

The process then repeats steps 2-4 according to the required number of layers to complete the multilayer structure.

During multilayer processing, the resin layer can still shift due to thermal expansion and contraction, causing tensile stress on the glass. A study by Shinko Electric Industries found that applying a resin edge coating on the glass substrate reduces edge stress. For example, a 300μm-thick resin layer creates about 95MPa of stress on the glass, but with edge coating, the stress can be reduced to about 49MPa.

To resolve the SeWaRe issue, various suppliers across the glass substrate process flow are actively rolling out solutions. For instance, Germany’s LPKF has introduced LIDE technology for TGVs. This technology involves laser-induced modifications followed by selective wet etching to form holes. Japan’s DISCO has launched its SD and LEAF laser dicing technologies, while Onto Innovation has released the Firefly G3, a metrology system for TSV inspection.

Supply Chain Dynamics

Currently, major semiconductor equipment and materials for glass substrate manufacturing are dominated by leading companies from Europe, the United States, and Japan. For instance, LPKF supplies TGV equipment; SCHOTT, Corning, AGC, and NEG provide low-CTE glass; Lam Research supplies etching and plating systems; DISCO specializes in dicing equipment; Onto and KLA offer inspection tools; and SUSS and EVG provide temporary bonders and debonders.

Glass substrate technology is advancing on multiple fronts. For a comprehensive analysis of key players and supply chain opportunities, access the full report: Intel's No SeWaRe Glass Substrates: TGV Challenges and Advanced Packaging Supply Chain Role

The arrival of the Nvidia Rubin generation is reshaping the demand structure for advanced substrate and PCB materials. Compared to its predecessor, the Rubin GPU substrate has seen significant increases in both area and layer count. Furthermore, cableless designs have catalyzed new demand for midplanes and orthogonal backplanes. The introduction of the Rubin LPX rack, a disaggregated rack for inference, has further expanded the overall consumption of high-end glass fiber cloth.

Related report: 2026 Outlook: NVIDIA Rubin Drives New Wave of AI Hardware Upgrades

On the supply side, however, the market faces severe constraints. Nittobo, the leading manufacturer holding approximately 90% market share in T-glass and 60-70% in NER-glass, is not expected to bring new capacity online until mid-2027 at the earliest. Consequently, critical material gaps cannot be filled in the short term. Glass fiber cloth has transitioned from a rarely discussed “supporting role” to a critical bottleneck affecting the lead times and costs of the entire AI server supply chain.

What is Glass Fiber Cloth and Why It Matters

Glass Fiber Cloth is a key raw material for Copper Clad Laminates (CCL), the primary component of PCBs. CCLs are formed by laminating glass fiber cloth, copper foil, and resin under high temperature and pressure, accounting for approximately 19%, 42%, and 26% of the total CCL cost, respectively. High-end CCL is categorized into grades ranging from M6 to M10, based on signal loss (from higher to lower loss).

In a CCL, these three components work together to reduce signal loss and achieve high-speed transmission:

• Glass Fiber Cloth: Utilizes Flat Glass Fabric technology and Low-Dk glass materials to narrow the velocity mismatch between glass fiber bundles and resin-filled gaps, thereby reducing signal loss caused by the Glass Weave Skew (GWS) effect, alternately known as the Fiber-Weave Effect (FWE).

• Copper Foil: Uses HVLP (Hyper Very Low Profile) copper foil with low surface roughness to create a smoother copper surface, reducing signal loss caused by the Skin Effect.

• Resin: Employs Low-Dk resins (such as PTFE, PPO/PPE) to minimize signal loss.

Depending on its Dk value, glass fiber cloth is classified into several grades: E-glass, T-glass (Low CTE), NE-glass (Low Dk), NER-glass (Low Dk2), NEZ-glass, and Q-glass. E-glass is the general-purpose electronic grade, while T-glass (Low CTE), NE-glass (Low Dk), NER-glass (Low Dk2), NEZ-glass, and Q-glass are specialty grades that attain lower Dk values primarily by tuning the SiO₂, Al₂O₃, and B₂O₃ composition.

T-glass (Low CTE) is used in IC substrates for GPUs and ASICs; NE-glass (Low Dk) is used in AI server motherboards and 400G switches; NER-glass (Low Dk2) is used in 800G switches; and NEZ-glass and Q-glass are used in 1.6T switches. As the grade rises, the price per unit area increases several-fold: the average selling price (ASP) of NE-glass (Low Dk) is about 6x that of E-glass, and the ASP of NER-glass (Low Dk2) is about 2.5x that of NE-glass (Low Dk).

For the next-generation Low Dk3 glass fiber cloth, Japan’s leading supplier Nittobo has developed an improved NEZ-glass, scheduled for release in 2027. Other suppliers are instead pursuing Q-glass, made from quartz fiber, to break through Nittobo’s technology barrier.

Q-glass is composed of 99.9% SiO₂, with Dk and CTE values far lower than those of existing glass fiber cloth. However, it faces challenges including very high price and extreme hardness that makes processing difficult. CCL makers are therefore expected to adopt Q-glass only in the early stages; as CCL formulations improve, NEZ-glass is expected to gradually replace Q-glass.

[Editor’s Note] To clarify, the potential transition from Q-glass to NEZ-glass is conditional — it depends on improvements in CCL formulations and Nittobo’s successful commercialization of NEZ-glass by 2027.

AI Is Driving Glass Fiber Cloth Demand on Multiple Fronts

T-glass (Low CTE)

T-glass features a Low CTE characteristic—as low as 2.8 ppm/°C, close to that of silicon (2.6 ppm/°C)—which effectively prevents chip warpage under thermal stress, and is particularly important in advanced packaging with multi-layer stacked structures. As a result, T-glass is used primarily in the substrates of AI chips such as GPUs and ASICs. As AI applications move into deployment, major CSPs are continuing to raise capital expenditure to procure general-purpose GPUs and custom ASICs, driving T-glass demand higher.

AI chip substrates are also growing in both area and layer count. Taking Nvidia GPUs as an example, substrate area has grown from 3,190 mm² in the Hopper series to around 4,780 mm² in the Blackwell series, and is expected to reach 8,000 mm² in the Rubin series, a roughly 2.5x total expansion from Hopper. Layer count has likewise risen from 14L in Hopper to 16L in Blackwell, and is projected to reach 18L in Rubin, a cumulative 30% increase.

Low Dk

Low Dk glass fiber cloth is used mainly in high-speed transmission applications such as AI server motherboards, UBBs, OAMs, switches, and routers. As per-lane rates on the Scale-Up and Scale-Out fabrics of AI servers move to 224 Gbps, the required CCL grade must be upgraded from traditional M7 to M8 or M9, boosting demand for Low Dk2 and Low Dk3 glass fiber cloth.

Furthermore, the layer counts for motherboards in each tray in AI server racks are increasing. During 2024 and 2025, layer counts were roughly 20 to 28, and are expected to reach 24 to 40 during 2026-2027.

To improve downstream assembly yields, Nvidia and AWS have also introduced cableless designs, making chip-to-chip transmission more dependent on high-end CCL and creating additional demand for midplanes and orthogonal backplanes.

Beyond AI servers used for training, disaggregated racks designed for inference have further driven PCB demand. For example, Nvidia announced at GTC in March 2026 the inference-oriented Groq 3 LPX rack, which houses as many as 32 compute trays per rack, further boosting demand for NER-glass (Low Dk2), NEZ-glass, and Q-glass.

Nittobo’s Capacity Bottleneck: Prices, Timelines, and the Second-Source Opening

Japan’s Nittobo is the leading glass fiber cloth supplier, with an integrated yarn-to-cloth production capability and advanced product technology. In Low CTE, Nittobo holds approximately 90% global share in T-glass. In Low Dk, Nittobo has stable mass-production capability for NER-glass (Low Dk2), with a global share of about 60%-70%.

To meet the strong T-glass and NER-glass demand driven by AI, Nittobo announced in August 2025 a plan to triple its T-glass capacity. During 2026-2027, Nittobo plans to invest more than ¥50 billion to significantly expand capacity in Japan and Taiwan. However, newly installed equipment typically requires about six months to reach stable yield, meaning meaningful relief of supply constraints is unlikely before mid-2027.

Because Nittobo holds a near-monopoly in the T-glass market, under severe shortage conditions, Nittobo raised prices across its glass fiber product line by 20% in August 2025, and plans another increase of roughly 20%-30% in April 2026. T-glass price hike will influence the price trends of downstream BT and ABF substrates. The impact is expected to be reflected in BT substrate quotes approximately one quarter after the hike, and in ABF substrates approximately two quarters after the hike.

Nittobo’s supply constraints are pushing downstream manufacturers to seek alternative sources, providing opportunities for second-source suppliers.

• Low Dk1: Asahi Kasei, Taiwan Glass, Fulltech Fiber Glass, Taishan Fiberglass, and Hong Ho have entered the market to compete for NE-glass share.

• Low Dk3: Suppliers like Asahi Kasei, Shin-Etsu, Glotech, Feilihua, Taishan Fiberglass, and Hong Ho are focusing on Q-glass, collectively capturing the majority share in the early stages of M9-grade CCL deployment.

• T-glass: Taiwan Glass, Fulltech Fiber Glass, and Hong Ho have developed corresponding products and passed customer validation.

The high-end glass fiber cloth market is tightening, and understanding the supply chain dynamics matters. For the comprehensive analysis on glass fiber cloth demand, pricing trajectory, and key suppliers, access the full report: 2026 T-Glass Supply Shortages: AI Rack Fiberglass Trend

The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.

Here’s what they said, and what it means for the structural shift in CPU:GPU ratios that we’ve been tracking.

Intel: The Ratio Is Already Shifting

During Intel’s Q1 2026 earnings call on April 23, CEO Lip-Bu Tan put a number on the shift:

The feedback from customers is that CPU is very important when they move from training to inference. The inference side — in terms of orchestration, control plane, and also managing all the different agents with data — CPU is much more efficient. The ratio of CPU to GPUs used to be 1 to 8, and now it’s 1 to 4, and I think towards parity or even better. The demand is very strong.

CFO David Zinsner mapped out the full range on the same call: training runs at roughly 7–8 GPUs per CPU; inference compresses that to 3–4:1; and for agentic and multi-agent workloads, the ratio could compress further, potentially even flipping in favor of CPUs.

Google: “General-Purpose Compute Is Going to Make a Comeback”

At Google Cloud Next 2026, Amin Vahdat, Google SVP and Chief Technologist for AI and Infrastructure, made a notable prediction about CPUs:

CPU will come back. Running these agents involves a lot of general-purpose compute — they’re orchestrating all the inference that’s going on. They create sandboxes, virtual machines to build code, run it, check the results, and then figure out the next set of outputs. So general-purpose compute is going to make a comeback.

The framing matters: this is not CPU replacing specialized accelerators, but CPU orchestrating them. Vahdat also noted that the age of purpose-built accelerators isn’t going away — specialization, he said, is going to continue.

TSMC: CPUs Are “More and More Important”

On April 16, TSMC Chairman and CEO C.C. Wei highlighted a key demand driver during the Q1 2026 earnings call: the shift from Generative AI’s query mode to Agentic AI’s command-and-action mode is leading to another step-up in token consumption, sustaining demand for leading-edge silicon.

On CPUs, Wei acknowledged they are becoming “more and more important” in today’s AI data centers. However, CPUs remain excluded from TSMC’s AI revenue calculation for a practical reason: TSMC currently cannot distinguish whether a CPU is destined for a PC, a desktop, or an AI data center. Wei noted the company may reconsider the definition in the future.

For the full analysis, see TrendForce's recent report, where we cover the competitive landscape across Intel, AMD, Nvidia, Arm, and the major CSPs, plus our projections on supply constraints and IC back-end design service opportunities.

2026 Agentic AI Wave: CPU Shortage and GPU Ratio Structural Changes

As AI data center clusters continue to scale, the demand for data movement has surged, pushing traditional copper interconnects to their physical limits. CPO is now widely regarded as one of the key interconnect solutions for next-generation AI infrastructure. With TSMC’s COUPE platform projected to enter volume production in 2026, CPO is making its transition from the lab toward commercialization.

However, the CPO inspection and testing phase remains a significant hurdle. Currently, the industry lacks unified standards, and processes remain largely manual, making testing one of the major bottlenecks holding back CPO chip mass production.

This article examines the technical challenges of CPO testing, provides a detailed breakdown of the four critical testing stages, and maps out the existing solutions and technical advantages of equipment vendors.

Related report: AI Interconnect Outlook: NVIDIA Leads the Transition to CPO and Silicon Photonics Architectures

What Makes CPO Testing So Challenging

Co-Packaged Optics (CPO) integrates optical components into a Photonic Integrated Circuit (PIC), which is then co-packaged with an Electrical Integrated Circuit (EIC) in a single chip. By replacing electrical traces with optical paths, CPO reduces power consumption and latency. The bonded PIC-EIC assembly is called an Optical Engine (OE).

TSMC’s COUPE (Compact Universal Photonic Engine) is one such implementation, using SoIC Face-to-Face (F2F) stacking to hybrid-bond the EIC directly onto the PIC, incorporating shallow dielectric vias (TDV), embedded microlenses, and metal reflectors.

Unlike traditional EIC testing, which is purely electrical, a PIC contains a large number of optical components such as couplers, modulators, photodetectors (PD), optical filters, and optical waveguides. Testing an OE requires expertise across electrical, optical, and optoelectronic interactions, significantly increasing test complexity.

PIC testing must measure parameters such as insertion loss (IL), polarization-dependent loss (PDL), responsivity, waveguide propagation loss, and optical crosstalk. However, there is currently no unified test standard for these.

In addition, precise alignment of optical probes is a major challenge. The technique of guiding external light from an optical fiber into the OE’s optical waveguide is called optical coupling. However, a single-mode fiber core has a cross‑sectional area of about 78.5µm², while that of an optical waveguide is only about 0.099µm², a difference of nearly 800 times. Without nanometer-level alignment precision, coupling loss will be enormous.

Therefore, the fiber array of the optical probe must maintain a precise gap from the wafer or die surface while finely adjusting its angle relative to the coupler to maximize optical power transfer, and then perform measurements sequentially across different wavelength ranges. Such delicate operations currently rely on manual handling, with 100% inspection of a single PIC taking on average more than 100 seconds, making this one of the key bottlenecks for mass production of CPO chips.

The Four Testing Stages, and Why OWAT Matters Most

The testing stages required for a single CPO chip are:

(1) PIC wafer‑level test: DC electrical and optical tests, such as basic optical measurements of power, loss, dark current, etc.

(2) EIC‑PIC wafer‑level test: modulation‑function tests (electro‑optic, opto‑electric, and opto‑optic), high‑speed tests, and S‑parameter measurements.

(3) OE‑level test: full‑flow calibration, DC tests, high‑speed tests, optical loop‑back tests, and S‑parameter measurements. This is the key stage for confirming “Known Good Optical Engines” (KGOE).

(4) Advanced‑package module‑level test: full system functional verification and optical loop‑back tests.

Among these, PIC wafer-level test, also known as OWAT, is the most critical stage. While PICs are typically fabricated on mature process nodes, EICs generally use advanced nodes. If defective PICs can be identified already at the wafer stage, before bonding with expensive EICs, then scrapping of EICs and subsequent process losses can be greatly reduced.

Competitive Structure of Supply Chain

Traditional EIC automated test equipment (ATE) market is dominated by Japan’s Advantest and the US’s Teradyne. Since developing CPO test equipment requires expertise in both EIC and PIC testing, both vendors have pursued partnerships with PIC probe specialists: Advantest with FormFactor, and Teradyne through its 2025 acquisition of Quantifi Photonics and collaboration with ficonTEC.

Advantest & FormFactor

In June 2024, Advantest, Jenoptik, and Ayar Labs jointly launched the UFO Probe Card, integrating both electrical and optical probes on a single card for simultaneous electro-optical testing. Its key innovation is alignment tolerance compensation technology: the optical probe’s output beam is specifically shaped, allowing the optical signal to enter the PIC coupler even with slight prober positioning errors, greatly reducing alignment time.

In April 2025, Advantest and FormFactor launched the V93000-Triton photonic test system, featuring 9-axis photonic alignment and FormFactor’s OptoVue Pro optical alignment system. Its CalVue technology enables in-situ calibration of Z-axis displacement and optical positioning by observing the fiber array via uniquely designed retro-mirror technology and applying automated machine-vision algorithms in real time, reducing fiber alignment time.

Teradyne & ficonTEC

In March 2025, Teradyne and Germany’s ficonTEC (now a subsidiary of China’s Robo Technik) announced the industry’s first high-volume 300 mm double‑sided wafer probe test system for silicon photonics. ficonTEC provides the WLT‑D2 double‑sided wafer test platform, which features 50 nm‑range precision alignment, while Teradyne supplies the UltraFLEXplus ATE and IG‑XL system software.

A key feature of ficonTEC’s WLT‑D2 is its dual‑sided test capability, enabling simultaneous electrical testing on the top surface and optical testing on the bottom surface of the wafer, thereby improving test efficiency. The subsequent DLT‑D1 is a dual‑sided die‑level test system that can connect up to three parallel test heads simultaneously, increasing throughput and reducing test cost. With the addition of the DLT‑D1, ficonTEC now offers a complete CPO test product portfolio from wafer‑level to die‑level.

Chroma

Chroma is the global leader in SLT equipment. Its photodiode burn‑in and reliability test systems, the Model 58604/58604‑C/58606 series, are designed for reliability testing of PIC components such as 3D sensing devices, LDs, PDs, and modulators. The Model 58606 provides 256 SMU channels per module layer, and can be configured with up to 7 layers, for a total of 1,792 channels. Leveraging its optical test expertise at the SLT stage, Chroma has also announced that it is investing in the development of CPO test equipment.

Keysight

Keysight, the global leader in measurement instruments, is well known for its high‑speed test equipment and also provides a complete PIC wafer‑test solution. Keysight’s PIC wafer‑test solution is integrated with FormFactor, and is compatible with FormFactor’s Velox prober control software.

Keysight’s N778x series polarization synthesizers can rapidly switch the incident light among different States of Polarization (SOP), and, together with the N7700100C Polarization Lambda Scan (LS) software, uses matrix methods to derive IL, PDL, TE/TM IL, and other parameters. Therefore, this solution does not need polarization‑maintaining fiber (PMF), nor does it require prior manual polarization correction at multiple wavelength points, greatly increasing test efficiency. In addition, its SOP stabilization technology can lock the input light’s polarization state at a specific point, ensuring stable optical coupling throughout the entire wavelength sweep.

Enlitech

In September 2025, Enlitech partnered with iST to launch Night Jar, a SiPh chip testing platform. Designed as an add-on hyperspectral imaging analysis system, it can be directly mounted onto probe stations of any brand across various testing stages (WAT, CP, FT, etc.). This platform addresses long-standing industry pain points: previously, light leakage locations in optical waveguides could only be roughly estimated using reflected light, yielding only total or average optical loss values.

The Night Jar platform is distinguished by its ability to precisely pinpoint light leakage and measure quantitative IL values for specific waveguide segments or optical components. By visually mapping these metrics and supporting wafer-level optical loss mapping, the platform enables R&D personnel to identify defects more accurately and rapidly, ultimately improving production yields.

Market Opportunities

As chip designs grow increasingly complex, the difficulty of SoC testing has risen significantly. The number of test stations and the overall testing time required for a single chip continue to increase, driving up the share of test equipment within total semiconductor equipment capital expenditures. As CPO chips are integrated into product portfolios, the semiconductor sector’s capital expenditures on test equipment are expected to climb even further.

The CPO test equipment market is taking shape, and knowing the competitive landscape matters. For the comprehensive supply chain and market analysis, access the full report:

CPO Testing Revolution: Market Opportunities in Co-Packaged Optics Validation

Meta Prioritizes Operational Readiness

Meta’s additional US$21 billion commitment to CoreWeave is driven by more than just compute capacity constraints; it is a strategic move to secure production-ready infrastructure that can immediately support inference and model serving. According to disclosures from both parties, this dedicated capacity will be deployed across multiple locations and will include some of the initial deployments of NVIDIA’s Vera Rubin platform, enhancing the performance, resilience, and scalability of Meta’s AI operations.

CoreWeave also noted that the core of this collaboration is to support Meta’s large-scale AI inference requirements. Meta is essentially procuring a comprehensive suite of cloud delivery capabilities optimized for AI workloads—comprising high-performance GPU clusters, networking, storage, and rapidly deployable infrastructure.

The expected advantages for Meta are threefold:

• Rapidly closing compute gaps for training, inference, and product deployment as frontier model competition intensifies;

• Securing early access to next-generation Rubin platform resources, avoiding the lead times of in-house data center build-out and equipment procurement;

• Externalizing part of the infrastructure build-out and delivery risk, allowing Meta to concentrate resources on model R&D and product execution.

In-House ASIC Development Continues; Training Chips Are the Primary Bottleneck

Meta has not abandoned its in-house ASIC development. In March 2026, the company unveiled a roadmap for the MTIA 300, 400, 450, and 500 series. The MTIA 300 is already integrated into ranking and recommendation systems, with subsequent generations set for phased rollouts. This indicates that Meta still views in-house ASICs as a critical mid-to-long-term strategy for reducing power consumption, lowering costs, and increasing platform control.

The primary bottleneck for Meta remains the development speed and maturity of its training chips for generative AI. Compared to inference chips, training chips are considerably more challenging in terms of architectural design, system integration, and mass-production validation.

Notably, chip development from tape-out to mass production is inherently expensive, time-consuming, and exposed to failure risk. Meta itself canceled one in-house chip program after small-scale testing, subsequently ramped up NVIDIA GPU procurement, and has reportedly leased Google TPUs to support model development. This underscores a key reality: ASICs can offer superior power and cost efficiency for specific, stable, and optimizable workloads. However, when applied to frontier model training and general-purpose generative AI compute, they still face significant challenges across architectural design, hardware-software co-optimization, manufacturing yields, development cycles, and ecosystem maturity.

Meta’s case illustrates that in the frontier AI race, merchant GPUs and cloud compute remain the most viable short-to-medium-term solutions, while in-house ASICs serve as a parallel, longer-term path for reducing costs and reinforcing platform control.

CPU’s Role in Agentic AI

Historically, CPUs have served as the “brains” of data center servers—handling complex logic, sequential processing, and classical machine learning workloads such as linear regression and decision trees.

The AI boom changed that dynamic. AI models now require massive parallel matrix multiplication, which GPUs—with their embarrassingly parallel architectures—are built to handle at scale. CPUs were relegated to compressing and routing memory data to GPUs. As a result, today’s AI data centers operate at CPU-to-GPU ratios of roughly 1:4 to 1:8.

Related report: 2026 Agentic AI Wave: CPU Shortage and GPU Ratio Structural Changes

The rise of AI agents is changing that balance. Unlike static LLMs, Agentic AI is designed to interact dynamically with its environment—planning tasks, calling tools, making decisions, and taking actions on behalf of users. The coordination layer that manages all of this—scheduling sub-tasks, routing tool calls, passing data between sub-agents, and evaluating whether the original request has been fulfilled—falls squarely on the CPU. This is what makes Orchestration a CPU-intensive workload.

Agentic RL adds further demand. When AI agents are trained through Reinforcement Learning (RL), each action the agent takes must be evaluated—a process that places additional load on the CPU.

A November 2025 paper, A CPU-Centric Perspective on Agentic AI, noted that CPUs remain crucial for tool processing tasks such as Python interpretation, web crawling, lexical summarization, and database searches—scenarios that remain prevalent in Agentic AI. AI Agents may face three primary bottlenecks regarding CPUs:

1. Latency: Tool processing on CPUs can account for up to 90.6% of total latency.

2. Throughput: Bottlenecks can stem from CPU factors (number of cores, coherence and synchronization) or GPU factors (main memory capacity and bandwidth).

3. Energy: CPU dynamic energy consumption can reach 44% of the total dynamic energy at large batch sizes.

To address these, the traditional CPU:GPU ratio must change. Arm estimates that while traditional AI data centers require about 30 million CPU cores per GW, demand will surge to 120 million CPU cores per GW in the AI Agent era—a fourfold increase. The future CPU-to-GPU ratio is expected to shift to between 1:1 and 1:2, significantly boosting market demand for CPUs.

CPU demand has surged across both AI workloads and general-purpose servers within data centers. Intel and AMD responded by raising prices across select CPU product lines toward the end of 1Q26.

Related report: Trends to Watch 2026: Agentic AI and Real-time Inference

2026 CPU Market Landscape

This demand shift is reshaping the competitive landscape. Beyond traditional server CPU vendors Intel and AMD, a new wave of non-traditional players—GPU maker Nvidia, IP licensor Arm, and major cloud service providers (CSPs) including AWS, Google, and Microsoft—are now entering the server CPU market.

Traditional x86 Vendors: Intel and AMD

Intel’s Xeon processors long commanded over 95% of the data center CPU market. That dominance began to erode in 2021, when yield issues with the Intel 7 process delayed the Xeon Sapphire Rapids launch by nearly two years, creating an opening for AMD’s EPYC Milan—built on TSMC N7 with the Zen3 architecture—to make meaningful inroads.

For 2026, Intel is planning two major launches, both on its most advanced Intel 18A process, reaffirming its commitment to in-house fabrication:

• Xeon 6+ (Clearwater Forest): Darkmont architecture, 288/288 cores/threads, TDP ~450W, featuring Foveros Direct Hybrid Bonding for the first time.

• Xeon 7 (Diamond Rapids): Panther Cove-X architecture, up to 256/256 cores/threads, TDP up to 650W.

However, due to ongoing yield issues with the 18A process, mass production for both may be delayed until 2027.

Meanwhile, AMD continues its partnership with TSMC. Its EPYC Venice, expected in 2026, will use the Zen 6 architecture, TSMC N2 process, and advanced packaging (CoWoS-L, SoIC), featuring 256/512 cores/threads. AMD is expected to continue gaining market share from Intel in 2026.

Arm-Based Entrants: Nvidia, Arm, Ampere, and the CSPs

In March 2026, Nvidia announced it would begin selling the Vera CPU as a standalone product, responding to customer demand for more flexible CPU:GPU configurations. Early partners include Alibaba, ByteDance, Cloudflare, CoreWeave, Crusoe, Lambda, Nebius, Nscale, Oracle, Together.AI, and Vultr.

Vera uses Nvidia’s custom Olympus architecture, along with TSMC N3 process and CoWoS-R packaging technology, and features 88 cores/176 threads with Spatial Multithreading. While its core count is lower than Intel or AMD flagships, it offers a 1.8 TB/s NVLink-C2C interconnect for memory sharing with Nvidia GPUs.

Related report: 2026 NVIDIA AI Outlook: From GPU to LPU Racks & Inference

Nvidia also introduced the Vera CPU Rack, built on its MGX architecture. A single rack features 32 × 1U compute trays, each housing 4 Vera CPU Nodes, totaling 256 CPUs (22,528/45,056 cores/threads and 400 TB of memory). These racks are interconnected via BlueField-4 DPUs—which integrate Grace CPUs and ConnectX-9—ensuring high integration within the Nvidia ecosystem.

Also in March 2026, Arm took an unprecedented step into the CPU product market with the Arm AGI CPU, ending 35 years of pure licensing. Built on TSMC N3 with the Arm Neoverse V3 architecture, it offers 136/136 cores/threads. Launch partners include Meta, Cerebras, Cloudflare, F5, OpenAI, Positron, Rebellions, SAP, and SK Telecom.

Arm has introduced standalone CPU racks in two configurations: an air-cooled version integrating 60 AGI CPUs (8,160/8,160 cores/threads, ~180 TB memory), and a liquid-cooled version supporting 336 CPUs (45,696/45,696 cores/threads, 1 PB memory).

Related report: Arm AGI CPU: Reshaping AI Data Center Architecture

Following the release of the 192-core AmpereOne and AmpereOne M, SoftBank-backed Ampere is expected to launch the AmpereOne MX in 2026, which will feature an increased core and thread count of 256/256.

Among the major U.S. CSPs, AWS was the earliest mover, launching its first in-house Graviton CPU in 2016 using the TSMC N16 process. In December 2025, it released Graviton5 on TSMC N3 (192/192 cores/threads). By pairing these custom CPUs with its Trainium 3 AI ASIC, AWS is able to effectively lower the costs of AI computation.

Microsoft became the second CSP to develop in-house CPU, debuting the Cobalt 100 CPU alongside the Maia 100 AI ASIC in November 2023 using TSMC’s N5 process. In November 2025, the company introduced the next-generation Cobalt 200, which utilizes the N3 process and provides 132/132 cores/threads.

Google followed suit in April 2024 with the launch of its first custom CPU, the Axion C4A, based on the TSMC N5 process. For 2026, Google plans to introduce the bare-metal Axion C4A.metal (96/96 cores/threads) and the next-generation Axion N4A (64/64 cores/threads), with the strategic goal of delivering the highest price-to-performance ratio in the market.

Below we summarize the core and thread counts of major CPUs in 2026. It is observable that the Intel Xeon 6+ (Clearwater Forest) will achieve the maximum core count of 288. This is followed by the AMD EPYC Venice, Intel Xeon 7 (Diamond Rapids), and AmpereOne MX, all of which feature 256 cores. However, due to the utilization of Simultaneous Multithreading (SMT) technology, the AMD EPYC Venice can execute 512 threads across its 256 cores, reaching the highest thread count currently available.

TrendForce expects the growing trend of major CSPs developing custom CPUs to create additional business opportunities for IC back-end design service providers. Currently, while AWS maintains its design in-house, both Google and Microsoft outsource their CPU back-end design services to Global Unichip Corp. (GUC). The following table summarizes the projected projects to be secured by ASIC design service providers between 2026 and 2028.