From a CapEx perspective, North American cloud service providers (CSPs) have significantly raised their 2026 capital expenditure guidance, with investment increasingly concentrated in the deployment of high-performance GPU clusters, in-house ASIC development, and next-generation data centers designed to support high-power-density computing.

In China, leading CSPs such as ByteDance and Alibaba are making equally substantial commitments to compute infrastructure. The continued rollout of the East Data West Computing (EDWC) initiative (which redirects eastern computing workloads to western regions to optimize data center distribution and promote balanced regional development) has positioned AIDCs as a core link between the digital economy and the modern power grid.

However, the three defining characteristics of AIDCs — high power density, extreme load volatility, and massive energy consumption — place immense pressure on power systems. To ensure the stable operation of compute workloads, energy storage systems have evolved from an “optional add-on” to “mission-critical infrastructure.”

The following analysis covers energy storage demand dynamics across North American and Chinese markets, as well as the energy storage solutions offered by major Chinese manufacturers. Insights on the Chinese market draw on TrendForce’s ongoing primary research and long-term coverage of the local industry.

North America and China: Different Challenges, One Common Need

The enormous power demands of AIDCs are driving regional grid loads sharply higher, widening energy supply gaps. North America and China face distinct challenges, but both are accelerating energy storage deployment as a result.

• North American Market: Grid Constraints and Gas Turbine Shortages Drive Urgent Storage Demand

North America is a core hub for global AIDC development, with electricity supply heavily dependent on natural gas — gas-fired generation accounts for 40–50% of the energy mix across most regions. Surging AIDC power demand has further tightened large gas turbine supplies. Faced with growing supply-demand imbalances and an escalating risk of grid outages, AIDC operators are under pressure to increase their share of renewable energy generation. However, the inherent intermittency and volatility of solar and wind power mean that robust energy storage systems are essential to guarantee 24/7 uninterrupted data center operations.

• Chinese Market: Policy Support and Resource Optimization Accelerate Storage Integration

China’s AIDC build-out is driven by national strategic initiatives, with optimizing regional resource allocation at its core. The government has incorporated “Computing-Power Synergy” (the coordinated planning of AI compute infrastructure and power systems) into new infrastructure projects, encouraging compute facilities to deploy advanced and grid-forming energy storage systems.

In practice, power grids in China’s eastern compute hubs are approaching their load capacities, while grid infrastructure in renewable-rich western regions remains relatively fragile. Ultra-high-voltage (UHV) transmission networks alone cannot fully mitigate the pulsed load shocks generated by AIDCs. Coupled with regulatory requirements for green electricity consumption, grid-forming energy storage and long-duration energy storage (LDES, predominantly 4–8 hours) have consequently become standard configurations for compute hubs, further accelerating the pace of energy storage integration.

Related report: Mutual Empowerment of AI Computing Power and Electricity: Power Grid, Long-Duration Energy Storage, and New Power System Transformation

AIDC Storage Demand on Two Fronts

AIDC energy storage is primarily deployed across two domains: the data center side and the generation side. On the data center side, during Large Language Model (LLM) training, AIDCs experience severe, pulse-like power transients that place extreme demands on power continuity and grid resilience. To address this challenge, NVIDIA's 800V DC architecture white paper highlights the need for a layered storage approach, leading to a two-tier deployment: external (facility-level) and internal (rack-level) storage.

• External (Facility-Level) Storage serves as reliable backup power, keeping grid load volatility under 2%; BESS can also participate in grid peak shaving and ancillary service markets. Additionally, they provide essential frequency regulation for on-site captive generation such as gas turbines and nuclear reactors.

• Internal (Rack-Level) Storage addresses immediate power anomalies within the facility. BBUs leverage DC-DC conversion for high efficiency, low parasitic power draw, and a compact form factor, suitable for distributed integration directly inside high-power-density AI server racks. Supercapacitors complement this by enabling instantaneous discharge of massive electrical transients with near-zero energy loss.

Related report: NVIDIA AI Server Power Roadmap & Data Center Build Risk

On the generation side, as the costs of solar modules and energy storage systems continue to decline, the levelized cost of energy (LCOE) for solar-plus-storage has fallen below that of conventional generation sources such as natural gas and nuclear power, giving solar-plus-storage a distinct cost advantage. As the green electricity transition accelerates AIDC adoption of renewable energy globally, energy storage systems play a critical role in ensuring stable alignment between variable renewable supply and the continuous, high-load power demands of data centers.

China’s Energy Storage Supply Chain: Accelerating Cell and Systems Technology Upgrades

This wave of AIDC-driven demand is accelerating technology development among Chinese energy storage manufacturers.

• Cell technology is advancing toward higher reliability, efficiency, and safety.

• Systems technology encompasses grid-forming storage, high-voltage DC (HVDC) architecture, liquid cooling, and long-duration energy storage.

TrendForce View

The global energy storage market in 2026 is entering a new phase of demand restructuring driven by AIDCs. Across the value chain, solar, wind, and storage are integrated on the generation side; grid-forming storage supports the grid side; and layered BESS, BBU, and supercapacitor protection covers the load side. At the dispatch level, AI-powered energy management systems (EMS) enable real-time matching of computing load and power supply. Together, these form a new type of infrastructure defined by the efficient synergy of computing power, electric power, and energy storage.

TrendForce believes that AIDCs will continue to provide steady growth momentum for the energy storage sector. Energy storage will play an increasingly critical role in securing compute reliability and advancing energy transition.

For an in-depth analysis and vendor breakdown, access our full report: 2026 Energy Storage Turning Point: AIDC Fuels Dual-Engine Demand Growth

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Against this backdrop, the competitive landscape for ASIC design and service providers is also changing. This article examines how NVIDIA and major CSPs are positioning themselves at the AI rack/POD scale, and how ASIC designers, including Broadcom, Marvell, MediaTek, Global Unichip (GUC), and Alchip, are leveraging interconnect technologies such as CPO to expand their reach from chip scale into the rack/POD scale arena.

Related report: AI Interconnect Outlook: NVIDIA Leads the Transition to CPO and Silicon Photonics Architectures

NVIDIA Expands Beyond the Chip to Every Layer of AI Infrastructure

First, a quick definition: an AI POD (Point of Delivery) is a standalone AI computing unit composed of compute nodes, networking, storage, and software. Scale-up interconnect (vertical scaling within a single system) is the technology that enables multiple chips, and even cross-rack configurations, to operate as a single unified system with ultra-low latency, forming the foundation for Rack/POD-scale integration.

As the primary unit of AI computing continues to expand, NVIDIA unveiled not only seven new Rubin-series chips at its March 2026 GTC, but also five MGX-series racks capable of integrating these chips into a single rack, and racks can be interconnected via switches to form a large-scale Vera Rubin POD.

To further strengthen its AI data center hardware portfolio, NVIDIA has in recent years secured key talent and technology licenses from memory-interconnect switch IC vendor Enfabrica and AI inference LPU vendor Groq, while also investing in quantum computing and optical-communication component suppliers, all in pursuit of pushing POD-scale performance to the extreme.

Related report: NVIDIA FY1Q27 AI Server Outlook: GB/VR Rack Leads

Google, AWS and Microsoft Build Proprietary AI Rack/POD around Efficiency

To improve AI computing performance, CSPs are not only adopting large on-chip SRAM in their inference chips, but also designing proprietary AI racks and PODs. Google has been the most aggressive, adopting its own scale-up technology ICI (Inter-Chip Interconnect) as early as 2017, introducing OCS (Optical Circuit Switch) in 2021, and planning to deploy its in-house Axion CPU and Boardfly network architecture in the TPU v8 series in 2026.

AWS plans to deploy its proprietary NeuronLink and Graviton CPUs in the 2026 Trainium3 UltraServers, while Microsoft plans to deploy an Ethernet scale-up network and Cobalt 200 CPUs in its Maia 200 POD. Meta takes a different approach entirely, adopting the open OCP (Open Compute Project) standard to build a standardized data center hardware ecosystem aimed at reducing overall costs.

Related report: 2026 AI Server Outlook: CSP Rack Power Scales Up

ASICs: Broadcom and Marvell lead; MediaTek, GUC and Alchip bet on CPO

The trend of CSPs independently designing AI racks/PODs has pushed ASIC design and service providers to expand beyond chip-scale offerings into rack/POD-scale solutions. For ASIC designers, this creates an entirely new incremental market.

Broadcom and Marvell have already built out comprehensive product lines spanning switches and NICs, while also taking an early lead in CPO technology. MediaTek, GUC, and Alchip are initially focusing on establishing strong track records in AI chip development, with plans to leverage CPO integration platforms as their path into the rack/POD scale market.

As shown in TrendForce’s product line overview, CPO is the technology track, aside from AI chips, that all six major companies have committed to investing in, signaling broad industry recognition that CPO has become one of the critical differentiators for next-generation AI rack/POD performance.

For an in-depth analysis of each vendor’s strategy and product roadmap, access our full report: ASIC Design and Service Competition Shifts from Chip Scale to Rack/POD Level.

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Apple’s entry in 2026 is expected to reinvigorate the foldable market. TrendForce estimates that Apple, leveraging its strong brand positioning and consumer anticipation, could capture nearly 20% market share in 2026, compressing the share of competitors such as Samsung Electronics and Huawei to around 30% each.

As for the technology itself, the competitive focus is shifting beyond hinge mechanics and structural optimization toward materials science. Foldable devices are entering a critical phase on the path toward creases that are truly imperceptible.

Related report: Quarterly Smartphone Market Status Update - 2Q26

From Foldable to Creaseless: Three Phases of Development

From Samsung’s crease-free display panel showcased at CES 2026 to OPPO’s recently launched Find N6, marketed around a “virtually crease-free” design, the industry’s appetite for a genuine breakthrough is clear.

Creases originate from the misalignment of the neutral layer within the panel stack, which causes localized tensile stress, leading to micro-cracks or permanent deformation under stress concentration. Solving this problem has driven the industry through three distinct phases of development.

Phase one (2019-2022): feasibility verification

The central question at this stage was whether a foldable device could fold reliably. Technical efforts focused on panel durability and hinge lifetime. Early products commonly used U‑shaped hinges, which forced the panel into a small bending radius when folded, causing strong stress concentration and deeper, more visible creases.

This then evolved into water drop hinge design, which increased the bending radius to distribute stress more evenly, significantly improving both panel lifetime and crease performance. Some manufacturers also introduced dual-track floating support structures that brace the panel from beneath when unfolded, helping the display lie flatter.

Phase two (2023-2025): structural optimization

At this phase, the focus was mass production and reliability improvement, with the goal of simplifying mechanisms and upgrading materials to improve assembly yield and overall product durability.

On the mechanical side, smartphone brands gradually reduced the number of components, optimized assembly processes, and introduced techniques such as welding, mortise-and-tenon joints, and 3D printing to improve overall production quality and consistency. On the materials side, they moved beyond traditional SUS stainless steel to aerospace‑grade alloys, carbon fiber, and reinforced composites, and began experimenting with novel materials like liquid metal to better balance strength and weight, enabling thinner, lighter, yet more durable product designs.

In addition, unified specs and design languages emerged: water drop hinges became the mainstream structural solution, clamshell and in-folding emerged as the two primary form factors, and key mechanisms such as sliders and cantilever supports settled into relatively fixed design architectures.

Phase three (2026~): material dominance

By 2024-2025, mechanical optimization had gradually approached its limits. Water drop hinges, floating supports, and multi-link designs — even with ever-higher precision — could make creases less noticeable, but could not make them truly disappear. This pushed the industry to rethink the problem at its core: a crease is not merely a structural issue, but the result of material deformation and fatigue under repeated stress.

Therefore, starting in 2026, the industry has shifted its focus toward materials engineering to actively regulate stress distribution and prevent bending stress from concentrating in a single region.

The crease problem is gradually moving from a visible defect toward something almost imperceptible — laying the foundation for a truly mature foldable product.

So what is actually driving this materials-led transformation? The answer lies in two key materials: UTG and OCA.

UTG: From Protective Layer to Core Mechanical Component

In the past, UTG was primarily used as a surface protective material, providing hardness, scratch resistance, and tactile feel. In next-generation foldable devices, it has become the structural core that defines how stress is distributed across the display stack.

The key design shift starts with thickness redistribution. Traditional homogeneous glass applies a single thickness across the entire panel, forcing a trade-off between strength and flexibility. Under a non-uniform thickness design, the folding area is precisely thinned to improve flexibility and reduce stress concentration, while non-folding areas maintain a greater thickness to preserve rigidity and impact resistance.

This design philosophy is also reflected in Apple’s foldable device patents.

Through chemical strengthening and multi-layer surface coatings, UTG’s resistance to cracking and fatigue has significantly improved, maintaining structural integrity under repeated folding. That said, UTG remains a high-modulus material whose primary function is to guide stress, not absorb it. Without an intermediary layer capable of absorbing and regulating stress, localized forces can still accumulate at layer interfaces, compromising long-term reliability.

OCA: From Adhesive Layer to Critical Stress Manager and Optical Interface

That intermediary layer is OCA (Optically Clear Adhesive). Once used primarily as an optical adhesive material for display modules, OCA has taken on a far more active role in next-generation foldable displays: dynamically distributing and buffering stress between material layers.

The key lies in the precise design of the material’s viscoelasticity, enabling it to exhibit distinctly different mechanical behaviors under varying strain conditions and time scales. During normal, gradual bending, OCA maintains a lower modulus, staying soft and allowing the stack to conform to deformation while absorbing stress, thereby reducing both fatigue accumulation and micro-crack formation. Under sudden impact, such as a drop or localized press, its modulus temporarily rises to provide structural support and prevent stress from concentrating in any single layer. The result is a material that is soft under everyday use and stiff when it needs to be.

Through these mechanisms, OCA helps stabilize the neutral layer and significantly reduce stress concentration during folding. Its micro-flow characteristics also allow it to fill microscopic irregularities formed over long-term use, reducing light scattering and further minimizing the visible crease.

TrendForce View

While material innovation now leads crease reduction, mechanical structures remain critical. The OPPO Find N6, for example, uses precision machining and 3D printing technologies to enhance hinge flatness, while polymer materials fill structural gaps to prevent localized suspension and stress concentration, ensuring stable deformation during repeated folding. Meanwhile, for the metal support plate behind the display, Samsung Display has adopted laser drilling technology to reduce hole spacing in bending areas, achieving a balance between structural rigidity and flexibility, and enabling a near crease-free visual experience.

Essentially, the key to crease improvement has shifted from hinge design to the coordinated management of material modulus, thickness distribution, and stress release. Only when unfolding leaves no trace will foldable phones truly reach the mainstream.

For a deeper dive into material stack design and foldable market forecasts, access the complete analysis here: Last Mile for Folding: Revolution of Crease from Mechanical Structures to Materials Science

In May 2026, Samsung Electro-Mechanics announced a silicon capacitor supply contract worth approximately USD 1 billion with a major global customer, covering deliveries through 2027 and 2028. A month later, the company outlined its strategic direction, pointing toward an integrated approach that bundles silicon capacitors, MLCCs, and package substrates. This reflects a broader market trend: silicon capacitors are emerging as vital complementary components for package-level power integrity.

What roles do silicon capacitors and MLCCs each play in power integrity, and how do they complement each other? This article examines the technical characteristics of both, and the supply chain dynamics.

Related report: MLCC Market Outlook 1Q26~2Q26

Power Integrity Moves Inside the Package

As GPUs’ thermal design power (TDP) rapidly escalates, components such as power shelves, VRMs, DC-DC converters, and OAM boards require significantly more MLCCs for filtering and voltage regulation so as to prevent voltage ripples from compromising computational stability. In the meantime, as AI accelerator platforms evolve to incorporate chiplets, HBM, and high-density advanced packaging, power integrity challenges are no longer confined to the PCB level; they are penetrating deeply into the package itself.

In a multi-die architecture, a single GPU package might house a compute die, an I/O die, and an NVLink I/O die. Together with HBM, silicon interposers, and package substrates, these components form a highly dense system. Every individual die and power domain necessitates an independent, rapidly responding decoupling network. Relying exclusively on board-level MLCCs creates excessively long current paths, introducing parasitic inductance that severely throttles transient response speeds.

Silicon Capacitors’ Advantages

Manufactured using semiconductor fabrication processes, silicon capacitors utilize a silicon substrate paired with thin-film dielectric materials like silicon oxide or silicon nitride. Unlike traditional MLCCs—which generate capacitance through alternating layers of ceramic dielectrics and metal electrodes—silicon capacitors align more closely with semiconductor manufacturing principles. They leverage techniques such as thin-film deposition, deep trench structures, and customized packaging to increase capacitance per unit area while minimizing parasitic inductance.

The defining characteristics of silicon capacitors are their exceptionally low equivalent series inductance (ESL) and their ability to be placed in close proximity to the chip. During high-load operations, the current demands of AI GPUs, CPUs, ASICs, and HBMs fluctuate rapidly within fractions of a second; minimizing ESL ensures the capacitor can rapidly compensate for instantaneous power demands and maintain rigorous power stability, which is precisely the core value of silicon capacitors for near-die decoupling inside the package.

A further advantage of silicon capacitors is their superior capacitance stability across high frequencies, temperature variations, and DC bias. In environments with high DC bias or elevated temperatures, MLCCs utilizing certain material compositions often suffer from capacitance degradation or unpredictable fluctuations. By contrast, silicon capacitors—benefiting from silicon-based thin-film dielectrics and precise semiconductor manufacturing—deliver exceptional capacitance stability and dimensional accuracy. This makes them highly suitable for applications requiring high-density mounting, rapid high-frequency response, and unwavering capacitance.

Related report: NVIDIA FY1Q27 AI Server Outlook: GB/VR Rack Leads

Different Jobs, Different Layers

MLCCs serve as the primary components for system-level power stability in AI servers, offering unparalleled advantages in cost, supply scale, maturity, and mass deployment. As AI servers transition into the Rubin generation, the simultaneous increases in GPU power consumption, HBM density, NVLink bandwidth, and high-speed networking chip requirements will continue to drive the expansion of MLCC usage. TrendForce notes that while a single NVIDIA GB200 board requires approximately 6,500 MLCCs, the next-generation Rubin architecture—featuring double the TDP and significantly more complex power management—will push per-board usage to roughly 12,000 units.

Silicon capacitors, on the other hand, provide a high-end solution for package-level power integrity in AI accelerators, excelling in low ESL, ultra-thin profiles, high-frequency stability, and custom integration.

Depending on placement requirements, silicon capacitors can be configured in top-side, land-side, or embedded formats, and positioned alongside GPUs, CPUs, or ASICs, at the bottom of silicon interposers, or embedded within the package substrate itself. The closer the capacitor is to the die, the shorter the current loop and the lower the parasitic inductance, which is critical for suppressing transient voltage fluctuations and high-frequency noise.

The relationship between MLCCs and silicon capacitors should therefore be understood as complementarity, not substitution.

Supply Chain Dynamics

MLCCs mainly use traditional passive component processes, dominated by established players such as Murata, SEMCO, Taiyo Yuden, and Yageo. In contrast, the silicon capacitor supply chain is more closely aligned with semiconductor processes and advanced packaging. TrendForce believes that the core competency for silicon capacitor vendors lies in their ability to co-design with AI GPU, ASIC, HBM, and packaging platforms, and to pass qualification by high-end customers. Overall, silicon capacitors carry higher entry barriers and longer customer qualification cycles, and the supply scale remains relatively limited.

Outlook: A Dual-Track Future

The key to silicon capacitors’ future growth is not to completely replace MLCCs, but to ride the rising penetration of advanced AI packaging and gradually become standard components inside GPU, ASIC, and HBM packages. However, several challenges remain, including cost and supply scale, customer validation cycles, and a high degree of design binding.

In the long term, capacitor demand in AI servers will evolve into a dual-track structure of board-level MLCCs and package-level silicon capacitors. MLCCs will continue to benefit from rising per-rack power consumption and growing demand for high-capacitance and high-voltage products, while silicon capacitors will benefit from PDN upgrades inside AI accelerator packages, tighter HBM integration, and the proliferation of chiplet architectures.

For a full analysis of silicon capacitor technology, supplier dynamics, and market outlook, access our report: Power Integrity Upgrades in AI Servers: Evolving Roles of Silicon Capacitors and MLCCs.

To address the surging KV cache storage demands of the AI inference era, Nvidia introduced the CMX Context Memory Storage Platform in January 2026, managed by the BlueField-4 DPU, which adds a pod‑level context tier between local SSD and shared storage.

Meanwhile, the rise of Agentic AI is reshaping CPU architecture. Jensen noted that agents live in a world of nanoseconds, where every moment of waiting prevents them from advancing to the next step, making ultra-low latency the primary requirement. With Nvidia and Arm both launching CPU rack solutions purpose-built for agents, the industry is shifting from throughput-oriented to latency-oriented architectures, opening up an incremental market for CPU RAM.

Related report: Server DRAM Industry Analysis－2Q26

Test-time Scaling “Thinking”: >5X Tokens Per Year

According to Nvidia’s public data, the average output token count per question has surged at a rate exceeding 5x per year since the second half of 2024, reaching approximately 30,000 to 40,000 tokens, indicating that the industry has entered the Test-time Scaling “Thinking” stage of Nvidia’s Three Scaling Laws. This explosion in per-question token output translates directly into greater demands on memory and compute resources.

In the AI inference era, hardware requirements for AI chips and overall systems differ fundamentally from those of AI training. Inference places three key demands on hardware: (1) higher queries per second (QPS), (2) longer context windows, and (3) more inference steps and agentic AI loops. Each of these drives structural changes in memory demand. We will examine this across three dimensions: model weights, KV cache, and agentic AI.

Related report: AI Servers Absorbing LPDRAM Capacity, Signaling Tight Supply as the New Norm

Model weights

Model weights are the numerical parameters stored within an AI model. When a model is loaded, these weights occupy a fixed portion of memory, which is a static allocation. The more parameters a model has, the more memory its weights consume. The formula for calculating model weight memory is:

Total Size of Model Weights = Parameters × bytes per parameter

KV Cache

KV cache stores the key-value vectors generated during the inference prefill stage, avoiding redundant computation during the decode stage, which is a dynamic allocation. As conversation length and batch size grow in inference workloads, KV cache memory consumption grows accordingly.

The formula for calculating the total size of KV cache is:

Total Size of KV cache (Bytes)

= 2 x number of layers x number of KV heads x head dimension

x sequence length x batch x precision (bytes)

SSD POD Demand Driven by KV Cache Offloading

As KV cache memory footprint expands dramatically with conversation length and batch size, its management and placement have become critical in AI inference applications. In long-context, high-batch workloads, when the GPU’s HBM capacity is insufficient, the system must discard KV cache and rerun prefill computation, increasing latency and raising total cost of ownership (TCO).

To address this, Nvidia released Dynamo, a KV cache offloading software, in March 2025. Dynamo offloads infrequently accessed KV cache to lower-bandwidth, higher-capacity, and more cost-effective tiers such as CPU RAM and SSD, ensuring this data remains reusable during the inference decode stage without requiring prefill recomputation.

Dynamo can be paired with the CMX Context Memory Storage Platform, which Nvidia introduced in January 2026, designed to store and manage the massive KV cache generated by long-context workloads. Built around the BlueField-4 STX Rack, CMX uses 64 BlueField-4 DPUs (4 BlueField-4 DPUs x 16 compute trays) to manage approximately 9,600 TB of capacity per rack, adding a pod‑level context tier between local SSD and shared storage.

Note: An SSD POD is a standalone storage unit comprising multiple SSD racks, dedicated to storing offloaded KV cache. Positioned as the G3.5 tier between local SSD (G3) and shared storage (G4), it provides greater capacity than local SSD (G3) for storing KV cache, while offering faster access speeds than shared storage (G4).

Agentic AI: More CPUs, More RAM

The proliferation of AI inference is also accelerating the deployment of agentic AI applications. In AI agent workflows, models must actively plan, call tools, make decisions, and execute actions on behalf of users, all of which require CPUs to handle orchestration, tool calls, data routing, and sub-agent evaluation. As a result, the CPU-to-GPU workload ratio in agentic AI deployments is expected to shift from a traditional ratio of 1:4 or 1:8 to approximately 1:1, creating significant growth potential for the CPU market and driving new demand for CPU RAM.

Related report: 2026 Agentic AI Wave: CPU Shortage and GPU Ratio Structural Changes

In 2026, Nvidia introduced the Vera CPU, purpose-built for agentic AI workloads. Based on the original specification, Vera supports up to 1.5 TB of LPDDR5X memory capacity, three times the capacity of the previous-generation Grace CPU.

Note: NVIDIA has decided to halve the SOCAMM memory capacity of its next-generation Vera Rubin Superchip modules, according to TrendForce’s latest findings. This adjustment does not reflect a reduction in NVIDIA’s overall memory demand. Rather, it is a response to insufficient LPDRAM capacity allocated to NVIDIA under its suppliers’ preliminary 2027 production plans.

Beyond Nvidia, the broader CPU landscape is also accelerating. Traditional x86 vendors Intel and AMD launched new products in 2026, with Intel’s Xeon 6+ (Clearwater Forest) and AMD’s EPYC Venice. On the Arm side, Arm launched the Arm AGI CPU, while Ampere’s AmpereOne MX is expected to enter mass production later this year. 2026 is shaping up to be the year of a full-spectrum CPU refresh for agentic AI.

In sum, we are seeing two new drivers of memory demand generated by AI inference. On one front, inference workloads are driving KV cache consumption to expand rapidly, and KV cache offloading technology enables large volumes of KV cache to be offloaded to CPU RAM and SSD POD. As Nvidia, Google, and others introduce new SSD POD platforms, demand in this segment is expected to continue rising.

On the other front, agentic AI is shifting the CPU-to-GPU workload ratio toward 1:1, creating significant growth potential for CPU demand and driving a corresponding increase in CPU RAM demand.

Related report: 2026 Trends: Memory for New AI Inference Demand

MediaTek - CPO IP & LPO AOC

Taiwan’s leading IC design house MediaTek has been aggressively expanding into optical interconnect. After announcing a US$90 million investment in silicon photonics (SiPh) design firm Ayar Labs in February 2026, MediaTek showcased its latest solutions at COMPUTEX 2026 in June. The company demonstrated a CPO technology capable of reaching up to 400 Gbps per fiber to illustrate its scale-up roadmap, alongside a Micro LED LPO AOC sample developed in collaboration with Microsoft Research for scale-out connectivity.

The CPO chip sample on display features an EIC designed in-house by MediaTek, with the PIC co-developed with Ayar Labs. Each fiber delivers up to 400 Gbps, with an 8 x 400 Gbps configuration enabling a 3.2 Tbps optical engine (OE).

Related report: CPO Testing Challenges: TSMC COUPE & Taiwan Supply Chain

MediaTek also integrates Microsoft Research’s MOSAIC Micro LED technology to deliver an Active Optical Cable (AOC) featuring an integrated LPO transceiver. In this design, Micro LED serves as the light source within the LPO transceiver, with each Micro LED operating at 2 Gbps. Approximately 150 Micro LEDs are combined to achieve 200 Gbps aggregate bandwidth (with redundant units included to guard against localized failures).

The Micro LED approach offers a “wide-and-slow” light source with lower power consumption, lower cost, and higher reliability compared with conventional VCSEL and DFB lasers.

Related report: 2026 Infrared Sensing Application Market and Branding Strategies - Micro LED CPO Market Value Analysis

GUC & Wiwynn - CPO Rack

ASIC design service provider GUC has also been actively expanding its optical interconnect capabilities. Following its collaboration announcement with Ayar Labs in November 2025, GUC entered a partnership with Wiwynn and Ayar Labs in May 2026 to jointly develop a rack-scale CPO solution, which was showcased at COMPUTEX.

The CPO rack integrates Ayar Labs’ TeraPHY OEs and ELSFP SuperNova light sources, delivering 800 TB/s of scale-up optical bandwidth across 64 GUC ASICs (32 compute trays) per rack via CPO. It also incorporates a fully liquid-cooled thermal architecture developed in-house by Wiwynn.

Also notable: in addition to GUC and Ayar Labs, Wiwynn disclosed its broader CPO supply chain partners at the show. These include AI chip design services firm Alchip; Detachable FAU suppliers Corning, SENKO, Browave, and FOCI; ELSFP module and connector suppliers Molex, TE Connectivity, and SENKO; and Optical Cable suppliers AFL, Corning, SENKO, Molex, and FOCI. The CPO rack sample on display used SENKO’s ELSFP module, Optical Cable and SN-MT connector.

Largan & AOET - PMLA & FAU

Largan Precision, the global leader in smartphone camera lenses, made its debut at COMPUTEX this year, exhibiting jointly with Ability Opto-Electronics Technology (AOET), of which Largan is the largest shareholder with approximately 15.2% stake. Leveraging its deep expertise in micro-optics design, Largan has developed its own optical coupling technology and unveiled first-ever samples of a multi-channel Photonic Module Lens Assembly (PMLA) and a 2D Fiber Array Unit (FAU).

The PMLA is an integrated optical component combining a prism and collimating lens to redirect the optical path and improve coupling precision. The 2D FAU uses stacked fiber routing to increase fiber density and improve alignment tolerance. The FAU sample demonstrated at the show supports 40 channels across four stacked layers, with 10 channels per layer.

Also worth noting: AOET displayed Metalens technology applicable to IR cameras and sensors, and announced plans to leverage its micro-glass processing capabilities to enter the FAU V-groove foundry segment.

AuthenX - FAU

AuthenX, a subsidiary of EZconn, showcased a Detachable 2D FAU and its application on a CPO chip. AuthenX’s Detachable 2D FAU (40-lens) is distinguished by its proprietary Metalens technology and optical coupling design, combined with a detachable architecture that simplifies maintenance and reduces the time required for repeated optical coupling operations.

LINTES – CPO/CPC Socket

LINTES, a subsidiary of LOTES, demonstrated a universal CPO/CPC socket and provided a live demonstration of CPC applications on-site. The socket is designed by LINTES and tooled for mass production by LOTES.

The CPO/CPC universal socket accommodates 12 Presslink Ultra CPC plugs. Each copper wire on the Presslink Ultra delivers 200 Gbps, with a single plug reaching an aggregate bandwidth of 3.2 Tbps. At this data rate, CPC transmission distance can reliably reach approximately 0.5 meters.

LINTES also displayed an optical engine set sample, an 800G LPO AOC sample, and an 800G OSFP Transceiver sample.

SK hynix - HBF & HBM & BlueField-4 STX

SK hynix presented a full product lineup covering the memory hierarchy for KV cache offloading (KV cache offloading will be explored in depth in our future article). At the G1 (GPU) tier, SK hynix displayed a schematic of its latest AI-N B (Bandwidth) product, which vertically stacks NAND to simultaneously achieve high memory capacity and bandwidth - also known as HBF (High Bandwidth Flash). In addition, SK hynix exhibited physical samples of each HBM generation from HBM2E through HBM4E.

Related report: Crossing AI Memory Wall: Storage Layer Reallocation and HBF Analysis

At the G2 (System Memory) tier, SK hynix showcased its LPDDR5X and DDR5 product lines. At the G3 (Local Storage) through G4 (Network Storage) tiers, the company also exhibited its SSD product line.

Notably, targeting NVIDIA’s newly added G3.5 (Context Memory Storage) tier, SK hynix displayed the PE9010 M.2 and PEB210 E1.S SSDs designed for use in BlueField-4 STX.

Samsung Semiconductor - HPB & HBM5

Samsung Semiconductor debuted a physical mockup of its next-generation HBM5. Of particular note, Samsung is set to adopt its proprietary HPB (Heat Path Block) thermal architecture in HBM5 for the first time, designed to address heat buildup in the Base Die under high-bandwidth operation.

The key design highlight of HPB is the addition of a separate chimney-like thermal structure directly on the D2D PHY responsible for HBM-to-GPU data transfer, allowing heat to be conducted out directly, thereby reducing thermal resistance and improving operational stability. Similarly, SK hynix’s previously announced iHBM platform plans to stack ICE (Integrated Cooling Elements) directly on the D2D PHY, which is expected to reduce thermal resistance by more than 30%. These designs are expected to indirectly drive an increase in HBM Base Die area in future generations.

Related report: 2Q26 HBM Market Dynamics and Forecast

Samsung Semiconductor also exhibited physical Core Die and Base Die samples for HBM4E and next-generation HBM (HBM5). Notably, the HBM4E Base Die uses Samsung’s 4nm process, while the HBM5 Base Die is expected to make a generational leap to Samsung’s 2nm process.

In addition, the company showcased its AI memory portfolio across the KV cache memory hierarchy, including the HBM4 at the G1 (GPU) tier, LPDDR5X at the G2 (System Memory) tier, PM1763 SSD at the G3 (Local Storage) tier, PM1753 SSD at the G3.5 (Context Memory Storage) tier, and PM9D3a SSD at the G4 (Network Storage) tier - going head-to-head with SK hynix.

HANMI Semiconductor - HBM Fluxless TC Bonder

HANMI Semiconductor, the leading manufacturer of HBM TC Bonders, exhibited its Wide TC Bonder designed specifically for next-generation HBM (HBM5 and HBM6). In addition to supporting larger die areas, the Wide TC Bonder can be optionally configured with a Fluxless version to improve bonding accuracy, filling the gap between conventional TC Bonders and Hybrid Bonders.

PSMC - WoW (Wafer-on-Wafer)

Taiwan-based memory manufacturer PSMC (Powerchip Semiconductor Manufacturing Corporation) presented under the theme “3D AI Foundry,” collaborating with partners including AP Memory, Syntronix, ESMT, and A.I. Memory to build a fully integrated ecosystem spanning IP, IC design, foundry, OSAT, and end applications. One of the highlights was its WoW (Wafer-on-Wafer) 3D stacking technology.

Unlike ESMT’s aiPIM, which focuses on vertically stacking DRAM dies on top of a larger Logic Die, WoW technology stacks an entire Memory wafer on top of an entire Logic wafer, improving bonding efficiency.

PSMC’s group partner A.I. Memory, an IC design company focused on AI-in-Memory technology, showcased AIM 3.0, its first product to adopt Hybrid Bonding. Due to its vertical stacking design, the chip footprint is compact, making it well-suited for small Edge AI devices such as IP cameras, where real-time facial recognition is supported.

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From Nvidia’s multi-billion dollar bet and the wave of startup launches to capital markets beginning to price these companies, it is clear that in the AI inference era, industry competition has shifted from building “bigger” models to “more efficient” models. This article will explore:

• The trend of AI shifting from training toward inference

• Architectural bottlenecks of general-purpose GPUs

• Advantages and challenges of hard-coded inference chips

• An overview of high-efficiency inference chip startups

Related report: NVIDIA FY1Q27 AI Server Outlook: GB/VR Rack Leads

Industry Shift: From Training to Inference

In the early days of generative AI’s rise in 2022, industry competition focused on model training. Whoever could train the most powerful model held the competitive edge, leading companies to pour massive capital into stacking parameters and chip resources in pursuit of leaps in model scale and capability.

However, as AI services enter routine deployment, the cost structure has changed. Unlike training, which is a high-capital but low-frequency R&D expense, inference is a high-frequency, long-term cost directly tied to revenue. Cost per token and energy efficiency directly affect gross margins and the ability to scale. Every API call and every generated token represents compute consumption and margin pressure. If token generation costs cannot decline with scale, the sustainability of the business model comes into question.

Consequently, the focus of hardware and software development has shifted toward throughput, energy efficiency, and memory architecture optimization, emphasizing data movement efficiency and low-latency design rather than simply pursuing peak compute performance.

Related report: NA CSPs Capex Surge Powers AI Infra Expansion

Architectural Bottlenecks of General-Purpose GPUs

Traditional general-purpose GPUs rely on HBM and external DRAM to store model weights, with compute cores physically separated from memory. Data must frequently move between the chip and the package. As inference traffic grows continuously, the architectural bottleneck of general-purpose GPUs becomes increasingly apparent.

For Transformer inference based on matrix multiplication, memory bandwidth and access latency are the primary constraints. While HBM provides high bandwidth, it comes with complex packaging, yield issues and high costs, and rising power consumption as bandwidth scales. For low-batch, low-latency requests, GPUs struggle to leverage their massive parallel advantage, leading to decreased utilization and higher costs per token.

On the other hand, as model scale is no longer the sole measure of competitiveness, the market has begun exploring ways to compress models while preserving inference capability. For example, 1.58-bit quantization and weight pruning enable models to maintain inference accuracy at extremely low memory footprints; Mixture-of-Experts (MoE) architectures reduce actual computation through a “partial activation” mechanism that activates only a small subset of expert sub-networks during each inference pass.

The rise of lean models opens a new direction for hardware design: when model weights and structure become stable and no longer require expensive dynamic memory to support flexibility, the path of embedding algorithms directly into silicon becomes commercially viable.

Related report: Crossing AI Memory Wall: Storage Layer Reallocation and HBF Analysis

Hard-coded Inference Chips: Advantages in Power, Cooling, and Capital Efficiency

Hard-coded inference chips emerged in response to efficiency bottlenecks. Vendors such as Taalas embed model weights in Mask ROM (Read-Only Memory) and use on-chip SRAM to handle dynamic data, drastically reducing the power consumed by external memory data movement and significantly improving tokens per watt and tokens per dollar. The primary benefits are low latency, low power consumption, and high throughput, with simplified cooling and packaging design.

However, the market’s primary concern remains hardware inflexibility in the face of rapidly evolving model updates. As a structural risk, specialized chips offer little room for adjustment compared to programmable architectures. Use cases must be highly stable and deployment scales sufficiently large to amortize non-recurring engineering (NRE) costs. The ecosystem also presents a meaningful barrier: cloud markets continue to rely on general-purpose platforms, and customers may prefer flexible solutions that can evolve alongside model upgrades.

To mitigate these risks, vendors are pursuing automated model-to-chip pipelines, pre-fabricated wafers, and hybrid programmable architectures integrating quantization and LoRA fine-tuning, striking a balance between hard-wiring and flexibility to enable commercial deployment.

Going forward, hard-coded technology is expected to gain traction in ultra-low-latency applications and closed-deployment scenarios where model structures are stable, privacy requirements are high, and deployment scales are well-defined. Hard-coded chips can operate in standard air-cooled racks, reducing energy consumption and capital expenditures, making them particularly attractive to cloud service providers and vertical integrators. Conversely, traditional ASIC vendors relying on software-compiled scheduling will face performance pressure at the architecture level.

Overall, TrendForce expects general-purpose GPUs to continue dominating training and multi-model environments. In mature, predictable inference scenarios, specialized architectures are expected to carve out their own space, not by displacing GPUs, but by addressing use cases where efficiency and cost structure matter most. The industry is thus evolving toward a dual-track structure where general-purpose and specialized computing coexist.

Taalas HC1: Proof of Concept for Hard-coded Inference

On February 20, 2026, Canadian AI chip startup Taalas launched the Taalas HC1, hard-wiring Llama 3.1 8B model directly into the chip, achieving a throughput of 16,960 tokens/s/user.

Moreover, the Taalas HC1 uses TSMC’s N6 process, requires no HBM memory or CoWoS packaging, and has a single-chip TDP of approximately 250W (air-cooled). Based on Taalas's analysis, compared to the Nvidia B200 (throughput optimized) running Llama 3.1 8B at a cost of 3.79 cents per million tokens, the Taalas HC1 achieves a cost of just 0.75 cents per million tokens, approximately one-fifth.

The key to Taalas’s compute efficiency lies in adopting the concept of Computing-in-Memory (CIM). CIM integrates compute functions within memory to perform computation directly within memory, eliminating the need for frequent data transfers between compute units and memory, thus removing the memory wall bottleneck, and reducing excess latency and power consumption during computation.

What is Computing-in-Memory? Since mathematician John von Neumann published the von Neumann architecture in 1945, chip design has followed a structure where components such as the Central Arithmetical (CA) unit and the Memory (M) unit are separate to maintain greater flexibility.

However, as the growth of memory bandwidth and computing power has become increasingly mismatched, the transfer of data between the computing unit and memory has become a major constraint. Computing-in-Memory (CIM) emerged to address this, evolving into various forms such as Digital CIM (DCIM), Analog CIM (ACIM), and Hybrid CIM. Nevertheless, the programming languages, underlying software architectures, and applications capable of running on CIM are not yet fully developed, and the technology remains in its early stages of development.

Compared to conventional CIM implementations, Taalas takes a more radical approach through hard-coding. Operating on the philosophy that “The Model is The Computer,” Taalas creates a fully hardware-defined AI hardcore model that embeds model weights directly into the chip’s Mask ROM. This captures the low-latency and low-power benefits of CIM while bypassing the bottleneck of CIM’s currently immature software ecosystem.

Beyond exceptional compute efficiency, by using high-density ROM to store model weights, Taalas can produce a dedicated chip for a new AI model by modifying just 2 mask layers — converting an AI model into a physical chip in just 2 months. Taalas also retains a portion of SRAM for KV cache and LoRA fine-tuning weights, compensating for the lack of flexibility.

Despite their different implementations, Taalas’s fully hardware-defined approach and Groq’s fully software-defined approach share the same goal: to achieve static scheduling and fully deterministic computation as much as possible, trading dynamic flexibility for maximum efficiency.

A New Era of Inference Chips: Diverse Technology Paths in Parallel

Beyond Taalas, a growing number of AI chip startups specializing in high-efficiency inference have entered the space, including Tenstorrent, Groq, Cerebras, SambaNova, MatX, Untether AI, Hepzibah AI, Etched, d-Matrix, Positron AI, Axelera AI, and FuriosaAI. Chip specifications across vendors are summarized below:

Implementation methods vary across Hard-Wired and CIM vendors. Taalas HC1 directly hard-wires model weights into Mask ROM (fully hardware-defined). Etched Sohu similarly uses a hard-wired architecture but applies to all Transformer models, offering greater flexibility. Within CIM: d-Matrix Corsair uses Digital Computing-in-Memory (DIMC) as its core technology, embedding the AI model’s underlying architecture into the chip, applicable to all AI models with even greater flexibility than Etched. Untether AI Boqueria uses at-memory compute, integrating RISC-V processors and processing elements directly within SRAM memory banks. Axelera AI Europa AIPU also uses Digital In-Memory Computing (D-IMC), with RISC-V controlling the data flow.

On May 14, 2026, Cerebras, currently the most talked-about name in the inference chip space, officially listed on the Nasdaq. Its core technology is Wafer-Scale Integration (WSI), which consolidates an entire 12-inch wafer into a single chip (WSE-3), delivering 44GB of on-chip SRAM and 21 PB/s of bandwidth. Cerebras has also secured a three-year compute partnership with OpenAI valued at over $20 billion and 750MW in capacity.

Currently, the market is in an early exploratory phase with multiple parallel tracks. Startups are simultaneously pursuing different technology paths, including Computing-in-Memory (CIM), SRAM-first architectures, wafer-scale integration, and tensor contraction processor. It is expected that future inference chip architectures will gradually integrate these various approaches to meet the performance and efficiency demands of AI inference.

In 2026, as AI data centers face growing power bottlenecks and EVs accelerate the adoption of high-voltage architectures, SiC and GaN technologies are increasing their share across global infrastructure.

This article explores the deployment of these technologies across AI/data center infrastructure and automotive and industrial systems, while providing insights into the evolving competitive landscape of the global supply chain.

Related report: 2026 AI Factory Infrastructure Outlook: HVDC Power & Liquid Cooling Trends

SiC/GaN Are Entering a Structural Growth Cycle

Driven by the global push toward smart grids, rising energy efficiency standards in AI data centers, and the accelerating adoption of high-voltage EV platforms, power devices are no longer peripheral components—they have become strategic essentials reshaping the global energy landscape.

Leading players such as Infineon, STMicroelectronics, onsemi, and ROHM Semiconductor are deepening vertical integration across the supply chain, transforming into full-stack energy management solution providers. This marks the entry of power semiconductors into a structural growth cycle.

Meanwhile, China’s power semiconductor industry has moved beyond the technology validation phase and is rapidly expanding thanks to national infrastructure strategies.

In 2026, competition will no longer center solely on performance. Instead, it will increasingly hinge on control over critical materials (such as high-quality crystal growth techniques) and advanced packaging capabilities (including silver sintering and pressure bonding).

As leading compound semiconductor technologies, SiC and GaN are driving breakthroughs in crystal growth, epitaxy, and wafer processing. These advances are accelerating the transition from discrete components to integrated modules, meeting market demand for extreme miniaturization and superior thermal performance.

Driven by both AI/data center infrastructure and automotive and industrial systems as dual growth engines, the market penetration of third-gen semiconductors is expected to continue to rise in 2026.

Related report: 2026 Global SiC Power Device Market Analysis Report

SiC is vital to the front-end and mid-stage power conversion within data center architectures, managing the highest voltages and power loads. With superior thermal performance and switching characteristics, SiC is essential for the development of next-generation solid-state transformers (SSTs).

Discussions regarding SSTs have intensified recently. SSTs can directly convert medium-voltage AC from the grid into the 800V DC required for AI infrastructure. Built on power electronics and wide-bandgap (WBG) semiconductor technology, SSTs serve as an alternative to traditional 50/60Hz transformers. Beyond significantly reducing footprint and improving energy efficiency, they offer precise, real-time control over power flow, potentially reshaping the design of medium-voltage power conversion systems.

From an application perspective, SSTs are suited to any scenario requiring efficient medium-voltage AC-to-DC conversion, including AI data centers, renewable energy systems, and EV charging infrastructure—making them a key direction for the next generation of power electronics upgrades. Driven by the extreme demands for power efficiency and density within AI compute clusters, SSTs are rapidly becoming the core solution for power supply transformation in future AI data centers.

Meanwhile, GaN, known for its high-frequency and high-efficiency properties, is becoming increasingly popular in mid- and end-stage power conversion. It supports ultra-high-power density and quick dynamic responses. Typical applications include AI server power units, data center PSUs, telecom power systems, and high-efficiency fast-charging devices. As the rapid proliferation of AI drives up power consumption and density requirements, HVDC architectures and high-efficiency conversion designs are becoming the industry standard. GaN components effectively reduce conduction and switching losses, allowing for significantly smaller magnetic components and a reduced thermal footprint.

Despite its advantages, GaN is still limited in ultra-high-voltage applications and extreme power density scenarios, where it must complement other wide-bandgap materials such as SiC. Furthermore, long-term reliability and durability standards for GaN in certain high-power applications still require further validation and standardization.

SiC/GaN in AI/Data Center Infrastructure

AI development has shifted from cloud-based training to large-scale inference applications, driving upgrades across servers, racks, power systems, and supporting infrastructure such as electrical systems and precision cooling (CRAC/CRAH). Even as AI chip process nodes advance to 2 nm and beyond, scaling alone is no longer sufficient to close the compute gap. Meanwhile, expansion is increasingly constrained by a physical “power wall,” turning AI competition into a fundamentally energy-driven race.

At the front end of power delivery, traditional AC architectures rely on multiple voltage conversion stages, each introducing significant thermal losses. In contrast, SiC-enabled HVDC architectures support direct high-voltage DC transmission, simplifying the conversion chain and minimizing energy loss. This enables a more efficient “grid-to-rack” power structure, forming a resilient and high-efficiency energy backbone for data centers.

At the rack and server level, GaN-based solutions can push power conversion efficiency beyond 96% to meet the highest titanium-level standards for energy efficiency. This translates into lower electricity costs, while significantly improving thermal headroom and power density within servers.

Related report: 2026 AI Server Outlook: CSP Rack Power Scales Up

SiC/GaN in Automotive and Industrial Systems

Global automakers are continuing to adopt 800V high-voltage platforms, driving the expansion of SiC power module capacity and contributing to cost reductions. Across mobility applications, including electric buses and trucks, this high-efficiency architecture is becoming a strategic foundation for improving driving range and charging speed.

Related report: 1Q26 Global Automotive Market Decode

For example, Tesla and BYD are enhancing energy efficiency across core vehicle models by adopting SiC chips and developing key power electronics in-house. Meanwhile, Hyundai and Kia have integrated SiC into their E-GMP platform, achieving a 5% increase in driving range alongside ultra-fast charging capabilities. Even in hybrid systems, Toyota has introduced SiC into the motor controller of its sixth-generation THS to improve PCU (Power Control Unit) efficiency and reduce power loss.

Market trends indicate that SiC and GaN technologies are driving convergence between energy systems and transportation infrastructure. GaN, in particular, is expanding beyond consumer electronics into automotive applications such as on-board chargers (OBC), DC/DC converters, LiDAR systems, and infotainment/audio amplifiers.

Leading companies, including Infineon, STMicroelectronics, EPC, Texas Instruments (TI), and ROHM, have already introduced automotive-grade solutions. For instance, Infineon has begun mass production of its CoolGaN 100V G1 automotive transistors and launched AEC-Q101-qualified GaN components.

Additionally, Tata Electronics has partnered with ROHM to focus on assembly and testing of automotive MOSFET power devices, linking local manufacturing capabilities with the global supply chain. This highlights the expanding structural role of power semiconductors within automotive systems.

Overall, SiC has become the standard specification for main traction inverters in 800V platforms or vehicle models with a driving range of 700km+. Meanwhile, GaN is entering a mass adoption phase. Although its penetration in main traction systems remains lower than SiC, GaN is increasingly favored in on-board charging, lightweight power modules, and LiDAR applications, where it helps reduce vehicle weight and free up interior space.

For a full analysis of the competitive landscape, access our report: SiC/GaN Power Semiconductors Break “AI Power Wall,” Reshaping Data Center Power Supply.

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The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.

As AI and HPC workloads drive chip packages to ever-larger form factors, the area utilization limits of circular wafers are becoming an increasingly important consideration. Panel-Level Packaging (PLP) addresses this directly by moving to square panels, which deliver higher area utilization and better alignment with large-die form factors.

Major foundries and OSATs including TSMC, Intel, Samsung, Rapidus, and Amkor are all advancing their PLP roadmaps. TSMC, through its subsidiary VisEra, plans to establish a CoPoS pilot line with trial production targeted for 2027, positioning 2026 as a critical window for product validation and deliveries for related equipment and material providers.

The central technical challenge, however, is warpage. As panel size grows and layer counts increase, thermal stress from CTE mismatches between materials compounds in ways that directly affect yield. To address this issue, specialty chemical suppliers such as AMC, WaferChem, and Everlight Chemical showcased corresponding solutions at Touch Taiwan 2026 in April. This article focuses on two key material approaches, Low-Temperature Curable PSPI and Balance Film, and maps out the current supplier landscape.

From Round to Square: The Rise of PLP

As AI model parameters grow exponentially, demand for computing performance continues to rise. With semiconductor process scaling approaching its physical limits, the industry has turned to assembling and stacking multiple chiplets on a single interposer to boost performance, driving a steady increase in package size. TSMC expects to achieve a 9.5x reticle size with its CoWoS-L packaging by 2027, while Intel plans to reach a 12x reticle size with its EMIB packaging by 2028.

Related report: Global AI Server & Supply Chain Outlook 2026

However, the continuous expansion of package sizes presents two major challenges: (1) the inefficiency of fitting square chips onto the edges of circular wafers, which reduces the area utilization rate for large-size packages; and (2) increasingly severe warpage issues, where warped sections of the substrate lead to poor contact.

To overcome these limitations, panel-level packaging (PLP) has come to the forefront. By transitioning from circular wafers to square or rectangular panels, chip edges can align seamlessly with the panel edges, thereby improving area utilization.

Currently, foundries, OSATs, material suppliers, and traditional LCD panel makers are all actively developing PLP technology. Mass production has been reached for relatively mature processes, such as the ones used to manufacture RF chips and PMICs (with an RDL L/S of approximately 10-20 μm). Conversely, advanced PLP processes for AI chips (with an RDL L/S of approximately 1-10 μm) have not yet entered mass production. Meanwhile, the industry is actively exploring both material and equipment solutions to address the warpage challenge.

What Causes Warpage and How to Fix It

The main cause of warpage is CTE mismatch between different materials, which generates stress differences during temperature changes and leads to bending. The magnitude of warpage is measured as the vertical distance between the highest and lowest points of the deformed surface, known as the peak-to-valley distance.

This problem increases non‑linearly with factors such as (1) larger panel area, (2) greater variety of materials, (3) larger CTE gaps between materials, (4) thinner thickness, and (5) more RDL layers. Whether the deformation appears as a concave ( “smiling face”) or convex (“frowning face”) profile, the result is poor contact between the chiplet and the panel.

Notably, the “chip-first” and “chip-last” processes in advanced packaging involve different warpage mechanisms, with variations in both timing and severity.

(1) Chip First：

The chip-first process comes in two variants: face-up and face-down. In the face-up approach, chips are mounted onto a glass carrier and encapsulated. The epoxy molding compound (EMC) is then ground down to expose the chip before the RDL is fabricated. In the face-down approach, the glass carrier is removed immediately after chip encapsulation, and the RDL is fabricated on the underside.

(2) Chip Last：

In the chip-last process, the RDL is fabricated on a glass carrier first, and the chip is mounted and encapsulated afterward. Because encapsulation occurs after RDL fabrication, the accumulated thermal stress is comparatively lower, making the assembly less prone to severe warpage. Furthermore, since chip placement occurs at a later stage, known good dies (KGDs) can be pre-screened and selectively placed, thereby improving overall packaging yields. Consequently, the chip-last process is predominantly utilized for high-end chip manufacturing, such as in TSMC’s CoWoS platform.

Materials and equipment providers have developed several solutions to address warpage. On the materials front, using a glass substrate as an interposer can resolve warpage at its source, as the CTE of glass (approximately 2.6 ppm/°C) closely matches that of silicon. However, glass is prone to micro-cracking (a.k.a. “SeWaRe”) during processing, and the supporting supply chain ecosystem is still developing.

Related report: Intel’s No SeWaRe Glass Substrates: TGV Challenges and Advanced Packaging Supply Chain Role

Alternatively, adopting low-temperature curable photosensitive polyimide (PSPI) as the interposer material can reduce processing temperatures and thereby mitigate warpage. However, it remains a significant R&D challenge to formulate a material that simultaneously offers low-temperature curability, a low CTE, a low dielectric constant (Dk), and high rigidity.

Another materials-based approach involves applying an anti-warpage balance film during processing to neutralize stress differentials. This resolves the warpage issue without modifying the core packaging materials. However, AMC is the sole supplier of high-end balance films at the present.

On the equipment front, thermocompression and vacuum suction can suppress deformation at the surface level, while selective laser modification alters the localized molecular structure within the material to relieve stress. However, surface-level suppression carries the risk of elastic rebound caused by residual stress once the panel leaves the equipment station, while selective laser modification remains largely in the R&D phase.

Material Solutions for Warpage Control

Low-Temperature Curable PSPI

Low-temperature curable PSPI reduces thermal stress accumulation by curing at below 250°C, significantly lower than the 300–350°C required for conventional PSPI. However, developing PSPI that simultaneously offers low CTE, low Dk, and high rigidity remains a significant R&D challenge. Conventional PSPI typically has a CTE of 40–80 ppm/°C and a Dk in the 2.8–3.6 range, far from the properties of glass.

Currently, most low‑temperature curable PSPI suppliers are Japanese companies such as Toray and FujiFilm. As the semiconductor industry shifts toward localized sourcing, Taiwan-based vendors are actively developing competing products, though achieving low CTE, low Dk, and sufficient tensile strength remains a challenge.

Balance Film

Balance film is formed by coating a base film with a special adhesive. When laminated onto a glass carrier or EMC, it generates a compensating stress in the opposite direction to offset thermal stress accumulated during processing.

The usage timing of balance film in a Chip Last process is as follows:

1. The RDL is first built on the glass carrier. A laser release layer is coated on the carrier to facilitate later separation, with no warpage at this stage.

2. A layer of balance film is pre‑laminated on the underside of the glass carrier to introduce warpage into the glass carrier as pre‑compensation.

3. As the RDL is built up layer by layer, the pre‑compensated panel is gradually pulled flat by the stress of the RDL layers; the balance film is replaced as needed until both the chips and EMC are completed, at which point there should be no warpage.

4. A layer of balance film is pre‑laminated on top of the EMC before de‑bonding the glass carrier, to avoid severe warpage that would occur if the glass carrier were removed directly.

5. After ball drop, dicing is performed; once the panel stress is released by dicing, the balance film is then removed.

A complete process thus requires at least two balance films (laminated on the glass carrier and the EMC respectively), with additional films added as RDL layer count increases.

If an optical engine (OE) is incorporated into the package, balance film can first be applied on top of the PIC to compensate for its larger warpage, followed by bonding the PIC to the substrate and then the EIC.

Warpage control has become a defining challenge as PLP scales toward advanced AI chip packaging. For a full analysis on the supplier landscape, access our report: Deconstructing PLP Warpage: Low-Temp PSPI, Balance Films, and Supplier Analysis.

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Related report: T-Glass Supply Shortages: AI Rack Fiberglass Trends

As AI chips grow more complex, package sizes keep expanding, and traditional organic substrates are reaching their limits. Under high temperatures during assembly, warpage reduces yield and becomes increasingly difficult to manage as package sizes grow.

Against this backdrop, glass, with better thermal and mechanical properties, is emerging as the next-generation material for advanced packaging. Glass-based solutions fall into two categories: one replaces the core layer of the substrate with glass, known as a glass core substrate; the other replaces the silicon interposer with glass, known as a glass interposer.

Intel has been an active mover in glass substrate technology. As early as 2023, Intel committed to glass substrates in its advanced packaging roadmap. In January 2026, it debuted the first sample combining EMIB packaging with a glass core substrate at NEPCON Japan — achieving No SeWaRe, or no micro-cracks — marking a decisive step toward commercial reality.

Meanwhile, Samsung and Rapidus are expected to roll out glass interposer solutions, while SK Absolics is targeting mass production of glass substrates in 2026.

This article covers the technical advantages of glass substrates, the manufacturing challenges that remain, and how the supplier landscape is taking shape.

Bigger Chips, Bigger Packaging Problems

As AI computing power requirements increase, the size of a single AI chip package is gradually expanding. Although ASML’s EUV (0.33 NA) currently limits the maximum reticle size to 26×33 mm (approximately 830 mm²), TSMC uses mask stitching technology to join multiple reticle patterns together in order to increase chip size.

Related report: Global AI Server & Supply Chain Outlook 2026

The single‑package size of NVIDIA’s Blackwell GPU is about 3.3× reticle size, roughly 2,739 mm². The next‑generation Rubin GPU is expected to expand to 4× reticle size, about 3,320 mm², while the Rubin Ultra GPU will reach 9× reticle size, about 7,470 mm². In addition to NVIDIA, Google’s TPU v9x (HumuFish) is also expected to adopt a large size of 9.5× reticle size.

According to TSMC’s CoWoS reticle size roadmap, the 5.5× reticle size variant is currently in mass production, with 9.5× targeted for 2027, 14× for 2028, and beyond 14× planned for 2029. Intel, meanwhile, is targeting a 12× reticle size EMIB solution by 2028 to address the demand for larger chip packages.

But scaling up package size introduces two key challenges.

First, square chips are increasingly hard to fit efficiently onto round wafers, which increases wasted area at the wafer edges. This led to the concept of panel‑level packaging (PLP), which uses square panels instead of round wafers, and is able to raise area utilization to over 75%.

Second, if large packages continue to use organic core substrate (mostly ABF materials made by laminating resin, glass fiber cloth, and copper foil), warpage during the reflow heating process becomes more severe, thereby reducing overall integration yield. (A deeper analysis of warpage challenges will be covered in our next article.)

Therefore, glass, which is flat in surface and is close to that of silicon (Si) in coefficient of thermal expansion (CTE), has become an ideal replacement for organic materials as an interposer or substrate.

Why Glass Substrates Outperform Organic Substrates

Simply put, better thermal, electrical, and physical properties.

• CTE close to silicon: Organic core substrates (OCS) have a CTE of roughly 7 ppm/°C, a significant mismatch with silicon’s 2.6 ppm/°C that could easily cause warpage. Glass, with a CTE of 3-9 ppm/°C, can be matched to silicon, maintaining stable yield even in large-size packages.

• Excellent dielectric performance: Glass is an excellent insulator. At 10 GHz, its dielectric constant (Dk) can be as low as 2.5-6, and its dielectric loss (Df) can be as low as 0.0005-0.005, allowing it to maintain signal integrity even in high‑speed transmission applications.

• Flat and smooth surface: Glass has extremely high surface flatness and smoothness, allowing it to achieve finer line width/spacing (L/S), such as <2 µm.

  

Who Is Building What, and When

As glass materials have excellent properties for advanced packaging, major foundries and OSATs are adding new product lines that use glass as either substrates or interposers.

TSMC unveiled its 310×310 mm CoPoS (Chip-on-Panel-on-Substrate) product line in 2025, and plans to establish a first mini production line at VisEra in 2026, begin small‑volume trial production in 2027, and reach mass production between 2028 and 2029. TSMC uses glass as an interposer in CoPoS, which requires a thinner profile (approximately 400 µm, roughly half the thickness of a substrate) and stricter CTE requirements, making it technically more challenging than glass used as a substrate.

Note: CoPoS replaces the traditional round glass carrier with a square panel format, improving interposer (RDL) utilization rates and eliminating the edge and corner area loss. (Updated June 2026)

Samsung announced at CES 2024 that it is developing glass interposer technology. In 2025, it established its first mini production line through SEMCO for glass core substrates, with mass production scheduled for 2027. Rapidus, meanwhile, showcased the largest glass interposer sample to date — measuring 600×600 mm — at SEMICON Japan 2025, with mass production targeted for 2028.

SK Group’s Absolics, a joint venture with Applied Materials, had already invested about KRW 300 billion in 2022 to build the first glass‑substrate factory in Covington, Georgia. Its goal is to develop glass substrates that can directly embed active/passive components, eliminating the interposer to reduce package area, thickness, and power consumption. The substrate measures 510×515 mm, with mass production planned for 2026.

Intel has been particularly active in glass substrate development. In September 2023, at Innovation Day, it announced plans to use glass substrates for advanced packaging, with mass production targeted between 2026 and 2030. On January 22, 2026, at NEPCON Japan, Intel showcased its first sample combining EMIB packaging with a glass core substrate. The package measures 78×77 mm (approximately 1,716 mm²), supports 2× reticle size, and uses a 10-2-10 stack structure (10 RDLs + 2 glass core layers + 10 RDLs, 22 layers total), with a total thickness of 800 µm and a bump pitch of 45 µm. Intel also reported achieving “No SeWaRe” (no micro-cracks) in testing, marking a decisive step toward mass production.

One Big Hurdle in Mass Production: SeWaRe

The biggest mass‑production challenge for glass substrates is “SeWaRe.” SeWaRe comes from the Japanese term 背割れ, meaning “back crack,” and refers to micro‑cracks that form during processing, especially drilling and dicing. As glass is brittle, micro‑cracks, once they appear, become stress‑concentration points that can cause the glass substrate to break during later testing and packaging steps.

As illustrated below, SeWaRe caused by dicing easily leads to near mode I fracture failure, which refers to the phenomenon where a material, under normal (perpendicular) stress, splits into upper and lower halves and fractures.

To reduce the probability of SeWaRe occurrence, the current mainstream glass substrate fabrication process includes:

1. Through-Glass Via, TGV: Typically, laser modification is first performed inside the glass, and then selective wet etching is applied to the modified regions to form TGV. TGV are X-shaped, because tapered sidewalls are better at distributing stress.

2. Polymer Lamination: A resin buffer layer is laminated onto the glass surface. Since copper (Cu) has a relatively high CTE, about 17 ppm/°C, the resin buffer layer prevents direct contact between the copper and the glass, avoiding cracking during thermal expansion and contraction.

3. Seed Sputtering: A metal seed layer is sputtered onto the surface.

4. Plating: A conformal metal layer is electroplated on the surface of the seed layer to reduce the amount of copper, and thereby prevent cracking during thermal expansion and contraction.

The process then repeats steps 2-4 according to the required number of layers to complete the multilayer structure.

During multilayer processing, the resin layer can still shift due to thermal expansion and contraction, causing tensile stress on the glass. A study by Shinko Electric Industries found that applying a resin edge coating on the glass substrate reduces edge stress. For example, a 300μm-thick resin layer creates about 95MPa of stress on the glass, but with edge coating, the stress can be reduced to about 49MPa.

To resolve the SeWaRe issue, various suppliers across the glass substrate process flow are actively rolling out solutions. For instance, Germany’s LPKF has introduced LIDE technology for TGVs. This technology involves laser-induced modifications followed by selective wet etching to form holes. Japan’s DISCO has launched its SD and LEAF laser dicing technologies, while Onto Innovation has released the Firefly G3, a metrology system for TSV inspection.

Supply Chain Dynamics

Currently, major semiconductor equipment and materials for glass substrate manufacturing are dominated by leading companies from Europe, the United States, and Japan. For instance, LPKF supplies TGV equipment; SCHOTT, Corning, AGC, and NEG provide low-CTE glass; Lam Research supplies etching and plating systems; DISCO specializes in dicing equipment; Onto and KLA offer inspection tools; and SUSS and EVG provide temporary bonders and debonders.

Glass substrate technology is advancing on multiple fronts. For a comprehensive analysis of key players and supply chain opportunities, access the full report: Intel's No SeWaRe Glass Substrates: TGV Challenges and Advanced Packaging Supply Chain Role

The arrival of the Nvidia Rubin generation is reshaping the demand structure for advanced substrate and PCB materials. Compared to its predecessor, the Rubin GPU substrate has seen significant increases in both area and layer count. Furthermore, cableless designs have catalyzed new demand for midplanes and orthogonal backplanes. The introduction of the Rubin LPX rack, a disaggregated rack for inference, has further expanded the overall consumption of high-end glass fiber cloth.

Related report: 2026 Outlook: NVIDIA Rubin Drives New Wave of AI Hardware Upgrades

On the supply side, however, the market faces severe constraints. Nittobo, the leading manufacturer holding approximately 90% market share in T-glass and 60-70% in NER-glass, is not expected to bring new capacity online until mid-2027 at the earliest. Consequently, critical material gaps cannot be filled in the short term. Glass fiber cloth has transitioned from a rarely discussed “supporting role” to a critical bottleneck affecting the lead times and costs of the entire AI server supply chain.

What is Glass Fiber Cloth and Why It Matters

Glass Fiber Cloth is a key raw material for Copper Clad Laminates (CCL), the primary component of PCBs. CCLs are formed by laminating glass fiber cloth, copper foil, and resin under high temperature and pressure, accounting for approximately 19%, 42%, and 26% of the total CCL cost, respectively. High-end CCL is categorized into grades ranging from M6 to M10, based on signal loss (from higher to lower loss).

In a CCL, these three components work together to reduce signal loss and achieve high-speed transmission:

• Glass Fiber Cloth: Utilizes Flat Glass Fabric technology and Low-Dk glass materials to narrow the velocity mismatch between glass fiber bundles and resin-filled gaps, thereby reducing signal loss caused by the Glass Weave Skew (GWS) effect, alternately known as the Fiber-Weave Effect (FWE).

• Copper Foil: Uses HVLP (Hyper Very Low Profile) copper foil with low surface roughness to create a smoother copper surface, reducing signal loss caused by the Skin Effect.

• Resin: Employs Low-Dk resins (such as PTFE, PPO/PPE) to minimize signal loss.

Depending on its Dk value, glass fiber cloth is classified into several grades: E-glass, T-glass (Low CTE), NE-glass (Low Dk), NER-glass (Low Dk2), NEZ-glass, and Q-glass. E-glass is the general-purpose electronic grade, while T-glass (Low CTE), NE-glass (Low Dk), NER-glass (Low Dk2), NEZ-glass, and Q-glass are specialty grades that attain lower Dk values primarily by tuning the SiO₂, Al₂O₃, and B₂O₃ composition.

T-glass (Low CTE) is used in IC substrates for GPUs and ASICs; NE-glass (Low Dk) is used in AI server motherboards and 400G switches; NER-glass (Low Dk2) is used in 800G switches; and NEZ-glass and Q-glass are used in 1.6T switches. As the grade rises, the price per unit area increases several-fold: the average selling price (ASP) of NE-glass (Low Dk) is about 6x that of E-glass, and the ASP of NER-glass (Low Dk2) is about 2.5x that of NE-glass (Low Dk).

For the next-generation Low Dk3 glass fiber cloth, Japan’s leading supplier Nittobo has developed an improved NEZ-glass, scheduled for release in 2027. Other suppliers are instead pursuing Q-glass, made from quartz fiber, to break through Nittobo’s technology barrier.

Q-glass is composed of 99.9% SiO₂, with Dk and CTE values far lower than those of existing glass fiber cloth. However, it faces challenges including very high price and extreme hardness that makes processing difficult. CCL makers are therefore expected to adopt Q-glass only in the early stages; as CCL formulations improve, NEZ-glass is expected to gradually replace Q-glass.

[Editor’s Note] To clarify, the potential transition from Q-glass to NEZ-glass is conditional — it depends on improvements in CCL formulations and Nittobo’s successful commercialization of NEZ-glass by 2027.

AI Is Driving Glass Fiber Cloth Demand on Multiple Fronts

T-glass (Low CTE)

T-glass features a Low CTE characteristic—as low as 2.8 ppm/°C, close to that of silicon (2.6 ppm/°C)—which effectively prevents chip warpage under thermal stress, and is particularly important in advanced packaging with multi-layer stacked structures. As a result, T-glass is used primarily in the substrates of AI chips such as GPUs and ASICs. As AI applications move into deployment, major CSPs are continuing to raise capital expenditure to procure general-purpose GPUs and custom ASICs, driving T-glass demand higher.

AI chip substrates are also growing in both area and layer count. Taking Nvidia GPUs as an example, substrate area has grown from 3,190 mm² in the Hopper series to around 4,780 mm² in the Blackwell series, and is expected to reach 8,000 mm² in the Rubin series, a roughly 2.5x total expansion from Hopper. Layer count has likewise risen from 14L in Hopper to 16L in Blackwell, and is projected to reach 18L in Rubin, a cumulative 30% increase.

Low Dk

Low Dk glass fiber cloth is used mainly in high-speed transmission applications such as AI server motherboards, UBBs, OAMs, switches, and routers. As per-lane rates on the Scale-Up and Scale-Out fabrics of AI servers move to 224 Gbps, the required CCL grade must be upgraded from traditional M7 to M8 or M9, boosting demand for Low Dk2 and Low Dk3 glass fiber cloth.

Furthermore, the layer counts for motherboards in each tray in AI server racks are increasing. During 2024 and 2025, layer counts were roughly 20 to 28, and are expected to reach 24 to 40 during 2026-2027.

To improve downstream assembly yields, Nvidia and AWS have also introduced cableless designs, making chip-to-chip transmission more dependent on high-end CCL and creating additional demand for midplanes and orthogonal backplanes.

Beyond AI servers used for training, disaggregated racks designed for inference have further driven PCB demand. For example, Nvidia announced at GTC in March 2026 the inference-oriented Groq 3 LPX rack, which houses as many as 32 compute trays per rack, further boosting demand for NER-glass (Low Dk2), NEZ-glass, and Q-glass.

Nittobo’s Capacity Bottleneck: Prices, Timelines, and the Second-Source Opening

Japan’s Nittobo is the leading glass fiber cloth supplier, with an integrated yarn-to-cloth production capability and advanced product technology. In Low CTE, Nittobo holds approximately 90% global share in T-glass. In Low Dk, Nittobo has stable mass-production capability for NER-glass (Low Dk2), with a global share of about 60%-70%.

To meet the strong T-glass and NER-glass demand driven by AI, Nittobo announced in August 2025 a plan to triple its T-glass capacity. During 2026-2027, Nittobo plans to invest more than ¥50 billion to significantly expand capacity in Japan and Taiwan. However, newly installed equipment typically requires about six months to reach stable yield, meaning meaningful relief of supply constraints is unlikely before mid-2027.

Because Nittobo holds a near-monopoly in the T-glass market, under severe shortage conditions, Nittobo raised prices across its glass fiber product line by 20% in August 2025, and plans another increase of roughly 20%-30% in April 2026. T-glass price hike will influence the price trends of downstream BT and ABF substrates. The impact is expected to be reflected in BT substrate quotes approximately one quarter after the hike, and in ABF substrates approximately two quarters after the hike.

Nittobo’s supply constraints are pushing downstream manufacturers to seek alternative sources, providing opportunities for second-source suppliers.

• Low Dk1: Asahi Kasei, Taiwan Glass, Fulltech Fiber Glass, Taishan Fiberglass, and Hong Ho have entered the market to compete for NE-glass share.

• Low Dk3: Suppliers like Asahi Kasei, Shin-Etsu, Glotech, Feilihua, Taishan Fiberglass, and Hong Ho are focusing on Q-glass, collectively capturing the majority share in the early stages of M9-grade CCL deployment.

• T-glass: Taiwan Glass, Fulltech Fiber Glass, and Hong Ho have developed corresponding products and passed customer validation.

The high-end glass fiber cloth market is tightening, and understanding the supply chain dynamics matters. For the comprehensive analysis on glass fiber cloth demand, pricing trajectory, and key suppliers, access the full report: 2026 T-Glass Supply Shortages: AI Rack Fiberglass Trend

The AI infrastructure buildout is reshaping supply chains at every layer. Join TrendForce experts and industry leaders at CompuForum 2026 on June 11 in Taipei to explore the strategic shifts ahead. REGISTER NOW.

Here’s what they said, and what it means for the structural shift in CPU:GPU ratios that we’ve been tracking.

Intel: The Ratio Is Already Shifting

During Intel’s Q1 2026 earnings call on April 23, CEO Lip-Bu Tan put a number on the shift:

The feedback from customers is that CPU is very important when they move from training to inference. The inference side — in terms of orchestration, control plane, and also managing all the different agents with data — CPU is much more efficient. The ratio of CPU to GPUs used to be 1 to 8, and now it’s 1 to 4, and I think towards parity or even better. The demand is very strong.

CFO David Zinsner mapped out the full range on the same call: training runs at roughly 7–8 GPUs per CPU; inference compresses that to 3–4:1; and for agentic and multi-agent workloads, the ratio could compress further, potentially even flipping in favor of CPUs.

Google: “General-Purpose Compute Is Going to Make a Comeback”

At Google Cloud Next 2026, Amin Vahdat, Google SVP and Chief Technologist for AI and Infrastructure, made a notable prediction about CPUs:

CPU will come back. Running these agents involves a lot of general-purpose compute — they’re orchestrating all the inference that’s going on. They create sandboxes, virtual machines to build code, run it, check the results, and then figure out the next set of outputs. So general-purpose compute is going to make a comeback.

The framing matters: this is not CPU replacing specialized accelerators, but CPU orchestrating them. Vahdat also noted that the age of purpose-built accelerators isn’t going away — specialization, he said, is going to continue.

TSMC: CPUs Are “More and More Important”

On April 16, TSMC Chairman and CEO C.C. Wei highlighted a key demand driver during the Q1 2026 earnings call: the shift from Generative AI’s query mode to Agentic AI’s command-and-action mode is leading to another step-up in token consumption, sustaining demand for leading-edge silicon.

On CPUs, Wei acknowledged they are becoming “more and more important” in today’s AI data centers. However, CPUs remain excluded from TSMC’s AI revenue calculation for a practical reason: TSMC currently cannot distinguish whether a CPU is destined for a PC, a desktop, or an AI data center. Wei noted the company may reconsider the definition in the future.

For the full analysis, see TrendForce's recent report, where we cover the competitive landscape across Intel, AMD, Nvidia, Arm, and the major CSPs, plus our projections on supply constraints and IC back-end design service opportunities.

2026 Agentic AI Wave: CPU Shortage and GPU Ratio Structural Changes

As AI data center clusters continue to scale, the demand for data movement has surged, pushing traditional copper interconnects to their physical limits. CPO is now widely regarded as one of the key interconnect solutions for next-generation AI infrastructure. With TSMC’s COUPE platform projected to enter volume production in 2026, CPO is making its transition from the lab toward commercialization.

However, the CPO inspection and testing phase remains a significant hurdle. Currently, the industry lacks unified standards, and processes remain largely manual, making testing one of the major bottlenecks holding back CPO chip mass production.

This article examines the technical challenges of CPO testing, provides a detailed breakdown of the four critical testing stages, and maps out the existing solutions and technical advantages of equipment vendors.

Related report: AI Interconnect Outlook: NVIDIA Leads the Transition to CPO and Silicon Photonics Architectures

What Makes CPO Testing So Challenging

Co-Packaged Optics (CPO) integrates optical components into a Photonic Integrated Circuit (PIC), which is then co-packaged with an Electrical Integrated Circuit (EIC) in a single chip. By replacing electrical traces with optical paths, CPO reduces power consumption and latency. The bonded PIC-EIC assembly is called an Optical Engine (OE).

TSMC’s COUPE (Compact Universal Photonic Engine) is one such implementation, using SoIC Face-to-Face (F2F) stacking to hybrid-bond the EIC directly onto the PIC, incorporating shallow dielectric vias (TDV), embedded microlenses, and metal reflectors.

Unlike traditional EIC testing, which is purely electrical, a PIC contains a large number of optical components such as couplers, modulators, photodetectors (PD), optical filters, and optical waveguides. Testing an OE requires expertise across electrical, optical, and optoelectronic interactions, significantly increasing test complexity.

PIC testing must measure parameters such as insertion loss (IL), polarization-dependent loss (PDL), responsivity, waveguide propagation loss, and optical crosstalk. However, there is currently no unified test standard for these.

In addition, precise alignment of optical probes is a major challenge. The technique of guiding external light from an optical fiber into the OE’s optical waveguide is called optical coupling. However, a single-mode fiber core has a cross‑sectional area of about 78.5µm², while that of an optical waveguide is only about 0.099µm², a difference of nearly 800 times. Without nanometer-level alignment precision, coupling loss will be enormous.

Therefore, the fiber array of the optical probe must maintain a precise gap from the wafer or die surface while finely adjusting its angle relative to the coupler to maximize optical power transfer, and then perform measurements sequentially across different wavelength ranges. Such delicate operations currently rely on manual handling, with 100% inspection of a single PIC taking on average more than 100 seconds, making this one of the key bottlenecks for mass production of CPO chips.

The Four Testing Stages, and Why OWAT Matters Most

The testing stages required for a single CPO chip are:

(1) PIC wafer‑level test: DC electrical and optical tests, such as basic optical measurements of power, loss, dark current, etc.

(2) EIC‑PIC wafer‑level test: modulation‑function tests (electro‑optic, opto‑electric, and opto‑optic), high‑speed tests, and S‑parameter measurements.

(3) OE‑level test: full‑flow calibration, DC tests, high‑speed tests, optical loop‑back tests, and S‑parameter measurements. This is the key stage for confirming “Known Good Optical Engines” (KGOE).

(4) Advanced‑package module‑level test: full system functional verification and optical loop‑back tests.

Among these, PIC wafer-level test, also known as OWAT, is the most critical stage. While PICs are typically fabricated on mature process nodes, EICs generally use advanced nodes. If defective PICs can be identified already at the wafer stage, before bonding with expensive EICs, then scrapping of EICs and subsequent process losses can be greatly reduced.

Competitive Structure of Supply Chain

Traditional EIC automated test equipment (ATE) market is dominated by Japan’s Advantest and the US’s Teradyne. Since developing CPO test equipment requires expertise in both EIC and PIC testing, both vendors have pursued partnerships with PIC probe specialists: Advantest with FormFactor, and Teradyne through its 2025 acquisition of Quantifi Photonics and collaboration with ficonTEC.

Advantest & FormFactor

In June 2024, Advantest, Jenoptik, and Ayar Labs jointly launched the UFO Probe Card, integrating both electrical and optical probes on a single card for simultaneous electro-optical testing. Its key innovation is alignment tolerance compensation technology: the optical probe’s output beam is specifically shaped, allowing the optical signal to enter the PIC coupler even with slight prober positioning errors, greatly reducing alignment time.

In April 2025, Advantest and FormFactor launched the V93000-Triton photonic test system, featuring 9-axis photonic alignment and FormFactor’s OptoVue Pro optical alignment system. Its CalVue technology enables in-situ calibration of Z-axis displacement and optical positioning by observing the fiber array via uniquely designed retro-mirror technology and applying automated machine-vision algorithms in real time, reducing fiber alignment time.

Teradyne & ficonTEC

In March 2025, Teradyne and Germany’s ficonTEC (now a subsidiary of China’s Robo Technik) announced the industry’s first high-volume 300 mm double‑sided wafer probe test system for silicon photonics. ficonTEC provides the WLT‑D2 double‑sided wafer test platform, which features 50 nm‑range precision alignment, while Teradyne supplies the UltraFLEXplus ATE and IG‑XL system software.

A key feature of ficonTEC’s WLT‑D2 is its dual‑sided test capability, enabling simultaneous electrical testing on the top surface and optical testing on the bottom surface of the wafer, thereby improving test efficiency. The subsequent DLT‑D1 is a dual‑sided die‑level test system that can connect up to three parallel test heads simultaneously, increasing throughput and reducing test cost. With the addition of the DLT‑D1, ficonTEC now offers a complete CPO test product portfolio from wafer‑level to die‑level.

Chroma

Chroma is the global leader in SLT equipment. Its photodiode burn‑in and reliability test systems, the Model 58604/58604‑C/58606 series, are designed for reliability testing of PIC components such as 3D sensing devices, LDs, PDs, and modulators. The Model 58606 provides 256 SMU channels per module layer, and can be configured with up to 7 layers, for a total of 1,792 channels. Leveraging its optical test expertise at the SLT stage, Chroma has also announced that it is investing in the development of CPO test equipment.

Keysight

Keysight, the global leader in measurement instruments, is well known for its high‑speed test equipment and also provides a complete PIC wafer‑test solution. Keysight’s PIC wafer‑test solution is integrated with FormFactor, and is compatible with FormFactor’s Velox prober control software.

Keysight’s N778x series polarization synthesizers can rapidly switch the incident light among different States of Polarization (SOP), and, together with the N7700100C Polarization Lambda Scan (LS) software, uses matrix methods to derive IL, PDL, TE/TM IL, and other parameters. Therefore, this solution does not need polarization‑maintaining fiber (PMF), nor does it require prior manual polarization correction at multiple wavelength points, greatly increasing test efficiency. In addition, its SOP stabilization technology can lock the input light’s polarization state at a specific point, ensuring stable optical coupling throughout the entire wavelength sweep.

Enlitech

In September 2025, Enlitech partnered with iST to launch Night Jar, a SiPh chip testing platform. Designed as an add-on hyperspectral imaging analysis system, it can be directly mounted onto probe stations of any brand across various testing stages (WAT, CP, FT, etc.). This platform addresses long-standing industry pain points: previously, light leakage locations in optical waveguides could only be roughly estimated using reflected light, yielding only total or average optical loss values.

The Night Jar platform is distinguished by its ability to precisely pinpoint light leakage and measure quantitative IL values for specific waveguide segments or optical components. By visually mapping these metrics and supporting wafer-level optical loss mapping, the platform enables R&D personnel to identify defects more accurately and rapidly, ultimately improving production yields.

Market Opportunities

As chip designs grow increasingly complex, the difficulty of SoC testing has risen significantly. The number of test stations and the overall testing time required for a single chip continue to increase, driving up the share of test equipment within total semiconductor equipment capital expenditures. As CPO chips are integrated into product portfolios, the semiconductor sector’s capital expenditures on test equipment are expected to climb even further.

The CPO test equipment market is taking shape, and knowing the competitive landscape matters. For the comprehensive supply chain and market analysis, access the full report:

CPO Testing Revolution: Market Opportunities in Co-Packaged Optics Validation

Meta Prioritizes Operational Readiness

Meta’s additional US$21 billion commitment to CoreWeave is driven by more than just compute capacity constraints; it is a strategic move to secure production-ready infrastructure that can immediately support inference and model serving. According to disclosures from both parties, this dedicated capacity will be deployed across multiple locations and will include some of the initial deployments of NVIDIA’s Vera Rubin platform, enhancing the performance, resilience, and scalability of Meta’s AI operations.

CoreWeave also noted that the core of this collaboration is to support Meta’s large-scale AI inference requirements. Meta is essentially procuring a comprehensive suite of cloud delivery capabilities optimized for AI workloads—comprising high-performance GPU clusters, networking, storage, and rapidly deployable infrastructure.

The expected advantages for Meta are threefold:

• Rapidly closing compute gaps for training, inference, and product deployment as frontier model competition intensifies;

• Securing early access to next-generation Rubin platform resources, avoiding the lead times of in-house data center build-out and equipment procurement;

• Externalizing part of the infrastructure build-out and delivery risk, allowing Meta to concentrate resources on model R&D and product execution.

In-House ASIC Development Continues; Training Chips Are the Primary Bottleneck

Meta has not abandoned its in-house ASIC development. In March 2026, the company unveiled a roadmap for the MTIA 300, 400, 450, and 500 series. The MTIA 300 is already integrated into ranking and recommendation systems, with subsequent generations set for phased rollouts. This indicates that Meta still views in-house ASICs as a critical mid-to-long-term strategy for reducing power consumption, lowering costs, and increasing platform control.

The primary bottleneck for Meta remains the development speed and maturity of its training chips for generative AI. Compared to inference chips, training chips are considerably more challenging in terms of architectural design, system integration, and mass-production validation.

Notably, chip development from tape-out to mass production is inherently expensive, time-consuming, and exposed to failure risk. Meta itself canceled one in-house chip program after small-scale testing, subsequently ramped up NVIDIA GPU procurement, and has reportedly leased Google TPUs to support model development. This underscores a key reality: ASICs can offer superior power and cost efficiency for specific, stable, and optimizable workloads. However, when applied to frontier model training and general-purpose generative AI compute, they still face significant challenges across architectural design, hardware-software co-optimization, manufacturing yields, development cycles, and ecosystem maturity.

Meta’s case illustrates that in the frontier AI race, merchant GPUs and cloud compute remain the most viable short-to-medium-term solutions, while in-house ASICs serve as a parallel, longer-term path for reducing costs and reinforcing platform control.

CPU’s Role in Agentic AI

Historically, CPUs have served as the “brains” of data center servers—handling complex logic, sequential processing, and classical machine learning workloads such as linear regression and decision trees.

The AI boom changed that dynamic. AI models now require massive parallel matrix multiplication, which GPUs—with their embarrassingly parallel architectures—are built to handle at scale. CPUs were relegated to compressing and routing memory data to GPUs. As a result, today’s AI data centers operate at CPU-to-GPU ratios of roughly 1:4 to 1:8.

Related report: 2026 Agentic AI Wave: CPU Shortage and GPU Ratio Structural Changes

The rise of AI agents is changing that balance. Unlike static LLMs, Agentic AI is designed to interact dynamically with its environment—planning tasks, calling tools, making decisions, and taking actions on behalf of users. The coordination layer that manages all of this—scheduling sub-tasks, routing tool calls, passing data between sub-agents, and evaluating whether the original request has been fulfilled—falls squarely on the CPU. This is what makes Orchestration a CPU-intensive workload.

Agentic RL adds further demand. When AI agents are trained through Reinforcement Learning (RL), each action the agent takes must be evaluated—a process that places additional load on the CPU.

A November 2025 paper, A CPU-Centric Perspective on Agentic AI, noted that CPUs remain crucial for tool processing tasks such as Python interpretation, web crawling, lexical summarization, and database searches—scenarios that remain prevalent in Agentic AI. AI Agents may face three primary bottlenecks regarding CPUs:

1. Latency: Tool processing on CPUs can account for up to 90.6% of total latency.

2. Throughput: Bottlenecks can stem from CPU factors (number of cores, coherence and synchronization) or GPU factors (main memory capacity and bandwidth).

3. Energy: CPU dynamic energy consumption can reach 44% of the total dynamic energy at large batch sizes.

To address these, the traditional CPU:GPU ratio must change. Arm estimates that while traditional AI data centers require about 30 million CPU cores per GW, demand will surge to 120 million CPU cores per GW in the AI Agent era—a fourfold increase. The future CPU-to-GPU ratio is expected to shift to between 1:1 and 1:2, significantly boosting market demand for CPUs.

CPU demand has surged across both AI workloads and general-purpose servers within data centers. Intel and AMD responded by raising prices across select CPU product lines toward the end of 1Q26.

Related report: Trends to Watch 2026: Agentic AI and Real-time Inference

2026 CPU Market Landscape

This demand shift is reshaping the competitive landscape. Beyond traditional server CPU vendors Intel and AMD, a new wave of non-traditional players—GPU maker Nvidia, IP licensor Arm, and major cloud service providers (CSPs) including AWS, Google, and Microsoft—are now entering the server CPU market.

Traditional x86 Vendors: Intel and AMD

Intel’s Xeon processors long commanded over 95% of the data center CPU market. That dominance began to erode in 2021, when yield issues with the Intel 7 process delayed the Xeon Sapphire Rapids launch by nearly two years, creating an opening for AMD’s EPYC Milan—built on TSMC N7 with the Zen3 architecture—to make meaningful inroads.

For 2026, Intel is planning two major launches, both on its most advanced Intel 18A process, reaffirming its commitment to in-house fabrication:

• Xeon 6+ (Clearwater Forest): Darkmont architecture, 288/288 cores/threads, TDP ~450W, featuring Foveros Direct Hybrid Bonding for the first time.

• Xeon 7 (Diamond Rapids): Panther Cove-X architecture, up to 256/256 cores/threads, TDP up to 650W.

However, due to ongoing yield issues with the 18A process, mass production for both may be delayed until 2027.

Meanwhile, AMD continues its partnership with TSMC. Its EPYC Venice, expected in 2026, will use the Zen 6 architecture, TSMC N2 process, and advanced packaging (CoWoS-L, SoIC), featuring 256/512 cores/threads. AMD is expected to continue gaining market share from Intel in 2026.

Arm-Based Entrants: Nvidia, Arm, Ampere, and the CSPs

In March 2026, Nvidia announced it would begin selling the Vera CPU as a standalone product, responding to customer demand for more flexible CPU:GPU configurations. Early partners include Alibaba, ByteDance, Cloudflare, CoreWeave, Crusoe, Lambda, Nebius, Nscale, Oracle, Together.AI, and Vultr.

Vera uses Nvidia’s custom Olympus architecture, along with TSMC N3 process and CoWoS-R packaging technology, and features 88 cores/176 threads with Spatial Multithreading. While its core count is lower than Intel or AMD flagships, it offers a 1.8 TB/s NVLink-C2C interconnect for memory sharing with Nvidia GPUs.

Related report: 2026 NVIDIA AI Outlook: From GPU to LPU Racks & Inference

Nvidia also introduced the Vera CPU Rack, built on its MGX architecture. A single rack features 32 × 1U compute trays, each housing 4 Vera CPU Nodes, totaling 256 CPUs (22,528/45,056 cores/threads and 400 TB of memory). These racks are interconnected via BlueField-4 DPUs—which integrate Grace CPUs and ConnectX-9—ensuring high integration within the Nvidia ecosystem.

Also in March 2026, Arm took an unprecedented step into the CPU product market with the Arm AGI CPU, ending 35 years of pure licensing. Built on TSMC N3 with the Arm Neoverse V3 architecture, it offers 136/136 cores/threads. Launch partners include Meta, Cerebras, Cloudflare, F5, OpenAI, Positron, Rebellions, SAP, and SK Telecom.

Arm has introduced standalone CPU racks in two configurations: an air-cooled version integrating 60 AGI CPUs (8,160/8,160 cores/threads, ~180 TB memory), and a liquid-cooled version supporting 336 CPUs (45,696/45,696 cores/threads, 1 PB memory).

Related report: Arm AGI CPU: Reshaping AI Data Center Architecture

Following the release of the 192-core AmpereOne and AmpereOne M, SoftBank-backed Ampere is expected to launch the AmpereOne MX in 2026, which will feature an increased core and thread count of 256/256.

Among the major U.S. CSPs, AWS was the earliest mover, launching its first in-house Graviton CPU in 2016 using the TSMC N16 process. In December 2025, it released Graviton5 on TSMC N3 (192/192 cores/threads). By pairing these custom CPUs with its Trainium 3 AI ASIC, AWS is able to effectively lower the costs of AI computation.

Microsoft became the second CSP to develop in-house CPU, debuting the Cobalt 100 CPU alongside the Maia 100 AI ASIC in November 2023 using TSMC’s N5 process. In November 2025, the company introduced the next-generation Cobalt 200, which utilizes the N3 process and provides 132/132 cores/threads.

Google followed suit in April 2024 with the launch of its first custom CPU, the Axion C4A, based on the TSMC N5 process. For 2026, Google plans to introduce the bare-metal Axion C4A.metal (96/96 cores/threads) and the next-generation Axion N4A (64/64 cores/threads), with the strategic goal of delivering the highest price-to-performance ratio in the market.

Below we summarize the core and thread counts of major CPUs in 2026. It is observable that the Intel Xeon 6+ (Clearwater Forest) will achieve the maximum core count of 288. This is followed by the AMD EPYC Venice, Intel Xeon 7 (Diamond Rapids), and AmpereOne MX, all of which feature 256 cores. However, due to the utilization of Simultaneous Multithreading (SMT) technology, the AMD EPYC Venice can execute 512 threads across its 256 cores, reaching the highest thread count currently available.

TrendForce expects the growing trend of major CSPs developing custom CPUs to create additional business opportunities for IC back-end design service providers. Currently, while AWS maintains its design in-house, both Google and Microsoft outsource their CPU back-end design services to Global Unichip Corp. (GUC). The following table summarizes the projected projects to be secured by ASIC design service providers between 2026 and 2028.