As CPO adoption expands from scale-out to scale-up, OE shipments are projected to grow significantly between 2027 and 2028, making the precision and capacity of the FAU coupling stage a key battleground for equipment vendors.

This article explains why FAU coupling has become a bottleneck and examines the equipment vendors competing to solve it, including ficonTEC, Suruga Seiki and TOYO Automation, GMT Global, All Ring Tech, and FitTech, along with key FAU, lens, and fiber suppliers.

Related report: CPO Technology Revolution: Next-Gen Interconnect for AI Data Centers

Two Coupling Paths for TSMC’s COUPE

At SEMICON Taiwan 2026, TSMC outlined an aggressive COUPE upgrade roadmap. Bandwidth per COUPE stands at 3.2 Tbps in 2026 and is expected to double to 6.4 Tbps by 2027, with a long-term target of exceeding 51.2 Tbps. TSMC also reiterated that integrating the OE onto the substrate can deliver 4X the energy efficiency of traditional copper interconnects and reduce latency to <0.1X. When the OE is further integrated onto the interposer (OOI), energy efficiency improves to 10X and latency drops to <0.05X.

From pluggable optics to CPO and OOI, the optical engine has steadily moved from the PCB into the package and closer to the compute die. Along the way, the FAU, which connects the optical fibers to the optical engine, has become part of the packaging process.

The FAU is a highly precise passive optical component that serves as an interface between optical fibers and the waveguides on the PIC. Its primary function is to align and secure the fibers so that light can be precisely coupled into the waveguides. Depending on the coupling architecture, the optical path may further incorporate microlenses/microlens arrays (MLAs), or other optical elements.

In silicon photonics chips, two of the most common ways to couple light between an optical fiber and the PIC are grating coupling (GC) and edge coupling (EC). A GC couples light in from the chip surface, which makes wafer-level optical testing easier, but it is typically more sensitive to wavelength and polarization. An EC instead guides light in through an optical facet on the side of the chip. It generally offers lower coupling loss and a wider operating wavelength range, but because the facet at the chip edge must be formed and accessed, wafer-level testing is more difficult.

TSMC’s COUPE supports both architectures. COUPE-GC combines a Si μlens, a Cu BMR (backside metal reflector), and a Si/SiN grating coupler to direct light into the PIC from above, while COUPE-EC couples light in from the side of the chip through an EC facet and a SiN tip. Both share common integration features, including SoIC bonding and TDV, and differ mainly in the optical coupling architecture between the fiber and the PIC.

Related report: 2026 New CPO Battleground: TSMC’s COUPE Roadmap Signals Opportunities for FAU Coupling Equipment

In the rest of this article, we break down why FAU coupling matters, why it has become a bottleneck, and how equipment vendors are positioning themselves in this market.

Read more

• Memory supply remains tight with no clear sign of relief. DRAM remains Very Tight at 20 weeks versus an 8-week balanced level, while shortages are limiting some NAND suppliers’ ability to support enterprise SSD solutions.

• Anthropic’s IPO filing puts a number on the AI infrastructure buildout: at least $518 billion. The long-term commitments span cloud computing, equipment and services, with roughly 80% non-cancelable or payable regardless of usage.

• Samsung is the next test for the memory upcycle. After Micron’s record quarter, Samsung’s Q3 preliminary results this week will show whether higher memory prices are still translating into earnings momentum, while its HBM4 ramp remains another key watch point.

01 / Supply Chain Radar

We track CPU, GPU, DRAM, NAND, HDD, ABF, and MLCC each week. Start with the status color, then compare the current lead time with the balanced-market benchmark and read the quick take.

02 / Last Week in Tech: Top 3 Industry Shifts

SEMICONDUCTORS / MEMORY

Micron Posts Record $54.2B Quarter, Sees No End to Memory Tightness

What Happened: Micron posted FQ4 revenue of $54.2 billion, up 31% QoQ, with non-GAAP gross margin reaching a record 87%, and guided FQ1 revenue to $61.5 billion. However, with contract prices rising from an already high base, sequential DRAM ASP growth eased to the high-teens percentage range. Meanwhile, Micron added 10 strategic customer agreements (SCAs), bringing its total to 26, some extending to 2031. These SCAs are expected to account for over 35% of revenue through 2030, underscoring the company’s decisive pivot toward long-term contracts.

Why It Matters: Management said it has no line of sight to when supply and demand will return to balance, projecting DRAM and NAND bit shipments to grow only in the low-20% and mid-20% ranges, respectively, through 2027–2028—with both markets still supply constrained. TrendForce believes the supply bottleneck remains structural amid AI-driven demand: cleanroom shortages, rising HBM trade ratios and diminishing gains from node transitions continue to constrain output. With more than 75% of Micron’s 2027 output already committed, supply is expected to remain tight in the year ahead.

AI / SEMICONDUCTOR

Anthropic Eyes $2T IPO as $518B Infrastructure Bill Ripples Through the Supply Chain

What Happened: Anthropic is preparing an IPO at a valuation of up to $2 trillion, with marketing now expected to begin the week of Nov 9 and a listing targeted before Thanksgiving (Nov 26)—later than the October timeline initially reported. Its filing shows 2025 revenue of about $4.6 billion, nearly 12 times 2024’s $386 million, alongside a net loss of roughly $42 billion, more than $34 billion of which stems from fair-value changes on debt rather than core operations.

Why It Matters: The filing puts a price tag on the AI buildout: Anthropic has committed at least $518 billion to infrastructure over the next decade, about 80% of it non-cancelable. The largest line is $161.2 billion in equipment leases with Broadcom, followed by Google ($111.1B), Amazon ($110B), xAI capacity ($84.5B), Microsoft ($31.4B) and AMD (over $20B), with Micron, Samsung and SK hynix named as memory partners.

AI / POLICY

Trump, AI Chiefs Sign Voluntary “Super Intelligence” Accord

What Happened: President Trump hosted a who’s who of tech leaders at the White House on Sep 29, where Meta, Nvidia, Google, OpenAI, xAI and Anthropic signed the “White House Accord on Super Intelligence: Joint Commitment on Frontier Responsibilities.” The roughly 300-word pact commits signatories to four layers of safeguards: internal controls that monitor model capabilities in areas such as cybersecurity and biosecurity, dedicated internal oversight teams, independent external auditors, and independent board committees to review their findings. Trump also announced plans for a 10-person AI safety committee and later named Jay Clayton to lead the new Super Intelligence Force.

Why It Matters: The accord is the administration’s clearest signal yet that it favors industry self-regulation over binding rules: Trump called it “morally binding,” but it carries no penalties, no requirement to disclose audit results and no government enforcement—even though OpenAI and Anthropic have publicly called for mandatory national safety standards. For now, that keeps compliance costs light and leaves the compute race untouched, as the text says nothing about chips, data centers, energy or export controls. But the document itself notes the steps may eventually be codified into law, and with Anthropic heading toward its IPO, independent audits and board-level safety committees could quickly become the governance baseline investors expect from every frontier lab.

03 / Week Ahead: Key Events to Watch

WED. OCT 7｜FOMC Minutes

Event: The Fed releases minutes from its Sep 15–16 meeting, where it raised rates by 25bp to 3.75%–4.00%, its first move after a five-meeting pause.

Why It Matters: The unanimous hike, paired with a hawkish dot plot pointing to a 4.1% year-end median, revived talk of a new tightening cycle. Since then, softer August core PCE (3.0%) and New York Fed President John Williams’ “no need for urgency” remarks have pushed markets toward a hold on Oct 28. The minutes will show which camp has the upper hand ahead of the Oct 14 CPI print.

Key Watch Points: One-and-Done or a New Cycle, Oil vs. Jobs:

Watch how many officials see another hike as necessary this year, and how much weight the Committee puts on rising oil prices versus cooling labor demand.

WED. OCT 7｜Applied Digital Reports Fiscal Q1 Earnings

Event: Applied Digital is scheduled to discuss its fiscal Q1 2027 results on October 7, with a conference call at 5:00 p.m. ET.

Why It Matters: Applied Digital has become a bellwether for the AI data-center buildout, with 1.4 GW of contracted critical IT load and approximately $36 billion in contracted base-term lease revenue as of its FY2026 year-end. Its results may offer an early read on whether AI demand is translating into energized capacity on schedule.

Key Watch Points: Leasing, Power and Financing:

Watch for new hyperscaler leases, the ramp at Polaris Forge 1, and progress on the 1.2 GW generation project being developed through Base Electron. Applied Digital reported $5.0 billion in debt and $4.2 billion in cash, cash equivalents and restricted cash as of May 31, 2026, making financing costs another key item to watch.

THU. OCT 8｜Samsung Reports Q3 Preliminary Earnings

Event: Samsung Electronics is expected to release preliminary Q3 results, with the latest FnGuide consensus at KRW 108.1 trillion in operating profit and KRW 201.7 trillion in revenue.

Why It Matters: Samsung is on track to top KRW 100 trillion in quarterly operating profit for the first time, up from KRW 89.5 trillion in Q2. Following Micron’s record quarterly revenue and stronger-than-expected outlook, Samsung’s results will offer another read on whether the memory upcycle is continuing—or whether slower price gains are beginning to temper earnings growth.

Key Watch Points: Profit Milestone, Memory Momentum, Currency:

Samsung expects Q3 HBM4 revenue to more than triple quarter on quarter and has begun shipping HBM4E samples. Watch whether higher memory prices are translating into stronger earnings, and how much of the profit growth is coming from Samsung’s memory business.

Ground Truth is a monthly TrendForce Substack column built on our proprietary Data Center Tracker, which covers major hyperscalers in the US and China, and monitors nearly 2,000 facilities worldwide. We cross-reference satellite imagery, permit filings, and utility records with our own supply chain research to deliver a first-hand, verified read on where hyperscalers are actually building AI capacity.

Each Substack issue includes:

• What’s Left to Build: a pipeline chart providing a macro view of each operator’s remaining build-out through 2030

• Monthly Capacity Tracker: a monthly scoreboard highlighting the biggest campus-level changes identified in our tracker

• Major Events: notable developments across the global build-out that readers should know about

Tracking scope

Includes self-built campuses, build-to-suit developments, and fully leased colocation. Excludes shared colocation, cloud regions, and power offtake agreements.

What’s Left to Build

How much data center capacity do the major hyperscalers still have to bring online, and how real are those plans? This chart answers both. Each bar represents an operator’s remaining path to their 2030 pipeline target, with capacity already online stripped out. The green segment is actively under construction, the lighter segment is permitted or planned capacity with an attributed power figure; permitted or planned sites we cannot yet size in MW are excluded, so this segment understates the true total. The grey is pipeline that hasn’t reached either stage yet due to possible delay or other complications. The wider the bar, the bigger the build-out ahead.

Key takeaways from the pipeline

Of the capacity we can size today, most is already under construction. Across the five operators, under-construction work makes up the bulk of the tracked 2030 pipeline, with only a small share still unstaged.

Delay risk looks low for now. Across the five operators, booked delays and unstaged capacity make up only a small share of the 2030 window, and where they appear they are tied to a few named sites rather than spread across the fleet. At the moment, hyperscalers are showing relatively few signs of delay risk or other build-out complications.

Monthly Capacity Tracker

Note: The figures in the monthly capacity tracker are changes to the capacity TrendForce carries in its tracking system, not capacity in operation. Each edition counts only changes whose trigger (a permit action, regulatory filing, construction contract, or operator announcement) is itself dated within the month. Capacity booked on earlier evidence is set aside.

This Month at a Glance

AWS led in total MW this month, driven largely by a single campus: Susquehanna, which accounted for nearly half. Google followed with revisions spanning three countries, led by a new 330 MW air permit in Omaha. Microsoft and Oracle recorded no in-window changes.

Major Events

Beyond the charts, here are some major developments we think are worth watching this month. These are the changes across the global build-out that the numbers alone don’t fully capture.

AWS is putting up data centers in months, not years

At its Madison County Mega Site outside Canton, Mississippi, AWS went from groundbreaking in May 2024 to five operating buildings by summer 2025. The next wave is moving even faster: according to a Madison County inspector, steel was up on seven Phase II buildings in late July 2026, and by September 6 satellite imagery shows a row of long, narrow halls already under roof, a visibly different building form from the square Phase I blocks next door.

Why it matters

AWS is openly pushing to industrialize construction. Its reported “Project Houdini” moves data hall fit-out into factories, cutting the time before servers can go in from about 15 weeks to 3. When shells rise in weeks and fit-out shrinks to days, the lag between capex and live capacity collapses, and schedules modeled on 18 to 24 month builds will run behind reality.

Google wraps up its Hamina expansion as the Nordics fill up with data centers

Google’s campus in Hamina, Finland, built inside an old paper mill on the Gulf of Finland, is finishing its seventh building this year. That takes the site to an estimated 300 MW, according to TrendForce’s tracker. In September Google also said it will spend at least €13 billion more in Finland in 2027 and 2028, split between Hamina and three new sites in Kajaani, Muhos and Vaala.

Why it matters

Across the five big US cloud companies, the Nordic capacity we track goes from about 1.4 GW this year to 3.3 GW by 2030. Power in the region comes mostly from hydro, wind and nuclear, and the cold climate keeps cooling costs down. Hamina pulls its cooling water straight from the sea and runs at a PUE of about 1.09. The new €13 billion program isn’t in those numbers yet, because Google hasn’t said how large the new sites will be.

ByteDance’s largest landlord raises its target in Shanxi

Chindata runs a 13-phase data center campus in Lingqiu county, Datong, with ByteDance as its anchor tenant. In September the company said it now plans more than 600 MW of IT capacity there, up from the “over 500 MW” it had cited before. More than 350 MW is already running, at an annual PUE below 1.18. Eight phases are operating, a ninth is being fitted out, and piling contracts for phase 10 were let this summer.

Why it matters

ByteDance says very little about how much capacity it is adding. Most of what we track for the company sits in leased or built-to-suit buildings, so updates like this one usually come from the landlord. This one raised the planned size of the site by about a fifth, and ByteDance itself said nothing.

Tencent’s Shaoguan campus clears its first construction milestone, and its next capacity may not be its own

Tencent’s Shaoguan campus in Guangdong passed the as-built check on Building 1 on 11 September, about a year after the structure topped out, while the city’s plan continues to list the project as under construction. Based on our reading of the latest city documents, we now expect the first hall to come online in 2027, with the full 90 MW following in 2028.

Why it matters

Shaoguan is the newest campus Tencent is building itself, and the only one still under construction. That isn’t Tencent stepping back from capacity, it is Tencent leaning on third-party operators instead, taking leased halls that arrive faster than a self-built site like Shaoguan. Our tracker shows additional Tencent capacity through third-party operators, and that capacity only becomes visible when the landlord discloses it, so Tencent’s real pipeline is larger than its own map shows.

• Server CPUs join the Radar this week, a sign of how fast agentic AI has moved them up the watch list. Lead times are at 25 to 30 weeks against a balanced 16 to 20, with major CSPs also accelerating their own in-house designs.

• The US and China extended their trade truce by two months, to January 10, after the Trump-Xi summit in Washington, while also agreeing to establish a bilateral AI dialogue.

• Micron reports fiscal Q4 this week, its first read since DRAM and NAND prices surged last quarter. The question is whether the memory rally still has room to run, with HBM4 progress the bigger test.

01 / Supply Chain Radar

We track CPU, GPU, DRAM, NAND, HDD, ABF, and MLCC each week. Start with the status color, then compare the current lead time with the balanced-market benchmark and read the quick take.

02 / Last Week in Tech: Top 3 Industry Shifts

AI / ECONOMY

Trump-Xi Summit Extends Trade Truce, Launches New AI Dialogue

What Happened: The U.S. and China wrapped up a three-day summit in Washington with several agreements aimed at stabilizing bilateral ties. The two sides confirmed a two-month extension of their trade truce through January 10, 2027, and agreed on more favorable tariff treatment for US$30 billion of non-sensitive goods in each direction. They also agreed to establish a bilateral AI dialogue, referred to by the U.S. as the U.S.-China Super Intelligence (SI) Dialogue, with the next exchange expected by November 2026. The two sides also agreed to establish a communication channel for AI-related incidents.

Why It Matters: The summit removes an immediate tariff escalation risk while creating more structured channels for trade, investment and AI discussions. But major disputes over technology restrictions and critical-mineral supply remain unresolved. With Trump and Xi expected to meet again at APEC in November and the G20 in December, the Washington summit looks more like another step in an extended negotiation than a final settlement.

AI / SEMICONDUCTOR

Meta’s Muse Ignites a CPU Rally, Extends into Hardware at Connect 2026

What Happened: Meta’s new AI agent Muse has reportedly out-downloaded ChatGPT in its first days on the market, and Wall Street is drawing a direct line to chip demand: because Muse runs on persistent cloud-based virtual machines, the market is betting agentic AI will lean far more heavily on CPUs than GPUs. The bet sent AMD, Intel and Arm surging in lockstep, with AMD crossing a $1 trillion market cap for the first time.

Why It Matters: Muse’s early momentum is quickly expanding beyond software. Its breakout comes as Meta kicks off Connect 2026 (Sept. 23–24), where the company is extending the assistant into hardware with Meta Charm, a compact handheld device built around Muse. With OpenAI reportedly developing a rival as competition with xAI’s Grok “teammates” intensifies, the agent race is widening—and so is the battle over the compute behind it. For chipmakers, the key question is whether always-on AI agents can sustain a new wave of CPU demand, or whether GPUs ultimately capture most of the upside.

SEMICONDUCTORS

Qualcomm Goes 2nm with Dual Flagship Chipsets

What Happened: Qualcomm entered the 2nm era at Snapdragon Summit on Sept. 22, unveiling a dual-flagship lineup — Snapdragon 8 Elite Extreme Gen 6 and Snapdragon 8 Elite Gen 6 — both built on TSMC’s 2nm process.

Why It Matters: Qualcomm’s move puts it just one week behind MediaTek, which launched its own 2nm Dimensity 9600 Pro on Sept. 15 — meaning Android’s two dominant chipmakers have both crossed into 2nm, with Apple’s A20 Pro also on the same node. The convergence hands TSMC a fresh wave of 2nm orders just as it ramps capacity. The chips also mark the first commercial validation of Samsung’s LPDDR6, confirming the new memory standard is ready to ship alongside next-gen silicon.

03 / Week Ahead: Key Events to Watch

TUE. SEP 29｜OpenAI DevDay

Event: OpenAI DevDay: Altman teases a big agent launch

Why It Matters: Shortly after Meta rolled out its Muse agent, OpenAI takes the stage as the agent race heats up. Altman posted on Sep 15 that a big launch was coming, then marked the event with six ship emojis, tech-speak for “we’re releasing something.”

Key Watch Points: New Model, New Pricing, New Agents

OpenAI is expanding its tools so AI agents can handle multi-step office work directly on its platform, and DevDay could show how far that goes beyond July’s Presence, which deploys agents in customer support, sales and billing. Watch for a next-generation model, a pricing or API overhaul that reshuffles the competitive landscape, and new platform capabilities such as autonomous agents.

WED. SEP 30｜Micron Reports Fiscal Q4 Earnings

Event: Micron reports fiscal Q4 results (ended Sep 3), coming off a record quarter as soaring memory prices reshape the DRAM and NAND markets.

Why It Matters: After DRAM and NAND ASPs surged by the low-60% and mid-80% ranges last quarter, Micron’s results will test whether the memory rally still has room to run—especially as LTAs lock in more supply amid lingering market uncertainty.

Key Watch Points: Margins, Supply Locked-In, HBM4 Catch-Up

Margins hit a record 84.9% non-GAAP in 3QFY26, best among the Big Three — the question is whether that holds. Micron has locked in 16 Strategic Customer Agreements, with markets watching for more. The bigger test is HBM4: still last in shipment share, Micron needs concrete progress to close the gap.

THU. OCT 1-2｜3D IC 2026 Conference

Event: 3D IC 2026 Conference takes place in Atlanta

Why It Matters: AI chips are outgrowing flat 2.5D packaging, so the industry is stacking upward into 3D while testing alternatives such as panel-level packaging. With TSMC, Rapidus and Kioxia on the program, the event offers a look at how leading foundries and memory makers plan to stack, connect and scale the next generation of AI silicon.

Key Watch Points: Panel-level Packaging, CMOS Directly Bonded to Array (CBA) for Memory

Beyond its 2nm push, Rapidus is reportedly developing packaging for both 300 mm wafers and 600 mm panels, while Kioxia is expected to detail CBA, the bonding technology behind its next-gen QLC 3D flash and a claimed 60% jump in bit density over its 8th-generation product.

Where KV Cache Lands

AI inference consists mainly of two stages:

• Prefill: The input prompt is processed in parallel in a single pass. The Key and Value vectors for each layer are computed and stored in the KV Cache, and the first output token is generated at the same time.

• Decode: Key and Value vectors are read from the KV Cache to generate tokens one at a time, while newly computed Key and Value vectors are continuously written back into it, until the response is complete.

This prevents models from recalculating all previous keys and values every time a token is generated.

As the context windows of AI users and batch size (including the number of AI agents in play) grow, the memory capacity required by KV Cache expands by multiples. The industry has therefore been developing KV Cache offloading technology and SSD POD to break through this capacity bottleneck.

KV Cache offloading moves cache that is temporarily unused or repeatedly readable from HBM, which is costly and limited in capacity, down to a lower-cost tier with more room.

An SSD POD is an independent storage unit formed by multiple SSD racks, sitting between local SSD and shared storage, and it extends the capacity available for holding KV Cache.

More on SSD POD:

Why QLC, and What it Costs

Read more

In the US, grid-deliverable capacity is not moving at the same pace, and by 2030 the distance between what the supply chain implies and what the grid can deliver is projected to exceed 170GW. The turn comes in 2028.

AI Servers Now Set the Data Center Power Budget

Global data center power demand capacity is projected to reach 161.0GW in 2026, up 31.0% YoY. This figure is expected to hit 211.1GW by 2027, sustaining a YoY growth rate of 31.1%. The largest growth driver? AI servers.

AI servers account for approximately 33.4% of total data center power demand capacity in 2026. That share could exceed 40% in 2027 and more than half (53.7%) by 2030. In absolute terms, AI server power demand capacity climbs from 53.8GW in 2026 to 127.1GW in 2028 and roughly 264GW in 2030, close to a fivefold increase in four years, against a 490.7GW global total.

General-purpose servers move the other way, with their share declining from around 40% historically to 25.6% in 2027, though in absolute power demand capacity they continue to exhibit growth, just far behind the much stronger growth shown by AI servers. Figures beyond 2027 are projections that rest on TrendForce’s AI chip and server shipment outlook and on the rising power draw of each new system generation.

Related report: Server Market Bulletin - Sep. 17, 2026

TrendForce notes that improvements to electrical and mechanical efficiency in data centers have reduced the additional facility load associated with each unit of IT power consumption. However, rapid deployment of IT equipment, led by AI servers, along with simultaneous growth in power demand from non-IT equipment, is prompting data center operators to begin planning for high-voltage direct current (HVDC) power architectures to improve end-to-end power distribution efficiency.

Demand and Delivery Separate after 2026, and the Gap Widens Greatly from 2028

Before 2025, the estimated data center power demand capacity and the actual power capacity that public grids could deliver closely tracked each other. However, supply and demand are expected to begin diverging in 2026, with the gap expected to widen significantly from 2028 onward.

By 2030, global data center power demand capacity is projected to hit 490.7GW, whereas the global grid-deliverable capacity will only reach 222.6GW (an upper bound that assumes grids outside the US fully deliver the data center demand), a gap of roughly 268GW.

TrendForce notes that this gap should be understood from two perspectives: First, data center electricity demand can be met not only by the grid but also through behind-the-meter (BTM), on-site generation developed by operators. Since this capacity is not included in estimates of grid capacity available to data centers, the calculated gap does not reflect the extent to which on-site generation could offset the shortfall. The headline gap may therefore be larger than the actual shortage.

Second, delays in grid interconnection and transmission and distribution infrastructure can create genuine power supply shortages.

In the US, which currently hosts the world’s largest concentration of data center deployments, a significant portion of data center demand through 2028 is expected to be grid-connected, with BTM emerging as an additional solution. Consequently, projects already planned for grid connection are likely to receive power on schedule.

However, after 2028, delays in grid power delivery are expected to become more frequent, substantially contributing to the growing gap between data center power supply and demand capacity. Setting TrendForce’s shipment-implied demand for the US, 272.4GW in 2030, against the 100.7GW that current grid data indicate can be delivered, the distance between the two will surpass 170GW by 2030. Whether this gap can be further reduced through additional behind-the-meter generation and grid power improvements remains uncertain.

How TrendForce Builds the Demand Line

The demand line does not start from announced campuses or utility filings. It starts from what the supply chain is shipping. TrendForce estimates server and AI chip shipments for each year, assigns each system generation its power draw, accumulates shipments into the fleet in service, totals the electricity that fleet consumes over a year, and converts it into power capacity. The reasoning is straightforward: a server that has been purchased will need power wherever it ends up, whether or not a grid connection is ready for it. Because TrendForce’s shipment data is global, the global total is then allocated to the US, China, and the rest of the world in proportion to the demand that public agencies forecast for each region. That places a little over half of the global total in the US, or 272.4GW in 2030.

As a reference point, the chart above includes the Reference Case from Lawrence Berkeley National Laboratory (LBNL), a US Department of Energy national laboratory. LBNL projects electricity use, and it equates its 2030 projection to about 148GW of interconnection capacity. TrendForce’s demand line sits well above LBNL’s. The difference reflects TrendForce’s supply chain view of AI server shipments and of the power each new system generation draws. The 272.4GW should therefore be read as the demand implied by equipment purchases.

In 2030, the distance of more than 170GW between TrendForce’s demand line and the grid-deliverable line is made up of two layers. The upper layer, about 124GW, is the amount by which shipment-implied demand runs ahead of the LBNL forecast. It is not a grid shortfall. It is demand beyond what that forecast anticipates, and it will have to be met through faster grid expansion, behind-the-meter generation, or deployment outside the US, or it will slip in time.

Below the LBNL line lies the portion of demand that the grid is not expected to deliver on schedule. TrendForce estimates this at approximately 49GW, derived region by region from the public filings of grid operators and utilities. TrendForce will continue to track grid operators’ filings and update this estimate as they change.

(Note: The above chart shows this portion as roughly 47GW, the distance between the LBNL line and the grid-deliverable line. That the two figures land close together, despite being derived differently, serves as a check on both.)

By region, PJM accounts for 19.5GW, ERCOT for 11.2GW, and MISO for 7.6GW, together representing 78.3% of the total. The deferral itself comes down to physical constraints: much of the US grid is aging, and the transmission, distribution and substation buildout needed to serve new load takes years to complete. These three markets are also where federal and state-level regulatory changes are most concentrated, and both phenomena point back to the same root cause: the volume of load interconnection requests has exceeded the speed at which existing rules, and the infrastructure behind them, can process them, prompting grid operators to pause and revise the rules before determining the order of energization.

Currently, the risk of delay is concentrated after 2028. Taking PJM as an example, load growth on PJM’s books is projected to rise from 5GW in 2025 to 29GW in 2030, while the deliverable baseline only reaches 9-10GW over the same period. The two lines cross in 2028, meaning that the volume of delays in 2026 and 2027 is too small to alter procurement decisions for those years. It is only after 2028 that a scale mismatch risk may emerge, where equipment has already been deployed but power supply may not yet be available to match it.

US State Regulation Now Moving as Fast as the Build-out

Until 2025, US hyperscalers have navigated relatively clear regulatory pathways in each state, but those regulations themselves are now changing at an equally unprecedented pace.

Over the past six months, public sentiment in the US towards data centers has plummeted, and local opposition has become a tangible barrier to project development. With 36 states holding gubernatorial races and 35 Senate seats up for election in the 2026 midterms, data centers have emerged as a mainstream political issue, with negative sentiment surrounding the construction boom spanning across party lines, a rarity in US politics.

Even in Texas, the state most data-center friendly in the country, Governor Greg Abbott sent a letter on August 3 to ERCOT and regulatory agencies requesting an audit of every data center in the interconnection queue; ERCOT subsequently suspended the Batch Zero interconnection study, which covers approximately 250 to 300 projects, with the review expected to take several months. Pennsylvania Governor Josh Shapiro, previously a major supporter of data centers, signed an executive order on August 18 removing all data centers from the state’s fast-track permitting process and barring them from re-entering.

The fact that two of the more supportive states tightened their policies in the same month indicates that this is not an isolated case but a widespread phenomenon during the election year.

Hyperscalers are the most capable of adapting to these regulatory changes, but deferral risks will still be amplified, particularly for projects still in the permitting and planning stages that have not yet broken ground. With rising regulatory uncertainty, operators may increasingly rely on BTM self-generation, though such approach comes with its own challenges, one of which is the lead time for generators and transformers.

What We’re Watching

Over the next six months, a large number of data center-related regulatory proposals are likely to emerge, ranging from symbolic measures to those that could pose real deferral risks. TrendForce will continue to track interconnection timelines across PJM, ERCOT, and MISO, the pace of BTM self-generation adoption, and state-level regulatory developments following the 2026 midterms, as the clearest early signals of whether the gap narrows or widens further.

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All Content is proprietary to TrendForce. Unauthorized reproduction, copying, distribution, or redistribution of this Content, in whole or in part, without the express written consent of TrendForce is strictly prohibited.

Copyright © 2026 TrendForce. All rights reserved.

• With demand picking up, NAND suppliers are reallocating capacity toward enterprise SSDs, though eSSD lead times remain elevated at 16 weeks against a balanced 8, as overall supply stays insufficient.

• SK hynix is reportedly in early talks with Intel to produce memory chips on U.S. soil. The supply chain question is whether this marks the start of South Korean memory makers manufacturing leading-edge chips overseas.

• Trump and Xi meet in Washington this week, with rare-earth export controls and AI chip restrictions on the agenda. Watch whether Washington eases chip export rules to China.

01 / Supply Chain Radar: Where the Six Sit This Week

We track GPU, DRAM, NAND, HDD, ABF, and MLCC each week. Start with the status color, then compare the current lead time with the balanced-market benchmark and read the quick take.

02 / Last Week in Tech: Top 3 Industry Shifts

MEMORY

SK hynix, Intel Reportedly Explore U.S. Memory Manufacturing Partnership

What Happened: SK hynix is reportedly in early talks with Intel to jointly produce memory chips on U.S. soil — either by leasing space at Intel’s long-delayed Ohio fab or forming a joint venture. The move would run alongside SK hynix’s existing Indiana HBM back-end packaging plant, slated to begin operations in 2029.

Why It Matters: If realized, this would mark the unprecedented debut of South Korean memory giants producing cutting-edge chips overseas. Beyond easing SK hynix’s U.S. expansion, a joint venture could pioneer a new co-investment model for CSPs to directly secure dedicated memory capacity in the AI era, though strict tech-export controls in Seoul still pose a major regulatory hurdle.

AI/ SEMICONDUCTOR

Huawei Fast-Tracks AI Chip Roadmap to Narrow Gap with NVIDIA

What Happened: Huawei has unveiled an accelerated Ascend roadmap as China doubles down on chip self-sufficiency. Following this year’s debut of the Ascend 950PR and 950DT, Ascend 960DT has been pulled forward by three quarters to early 2027, with the 960PR also moving up a quarter to 3Q27 — narrowing China’s timeline in catching up with NVIDIA.

Why It Matters: Huawei’s push hinges on a critical unknown: whether it can scale AI chip output without direct access to HBM, relying instead on in-house memory alternatives HiBL and HiZQ. And while DeepSeek’s reportedly plan to deploy at least 160,000 Ascend 950DT chips signals growing traction, its continued reliance on NVIDIA GPUs for training shows Huawei’s chips have yet to prove themselves in the most demanding, compute-intensive workloads.

AI / SERVER

Apple Mulls Potential Return to Server Market

What Happened: Under new CEO John Ternus, Apple is reportedly exploring a return to the enterprise server market, marking a potential new frontier for its in-house silicon push. The systems could be powered by M8 Ultra chips, Apple’s highest-performance processors.

Why It Matters: A confirmed launch would mark several milestones for Apple’s silicon strategy. First, its most powerful chips — long confined to consumer devices — would finally be built for the enterprise. Second, selling those systems to outside customers would revive a business Apple walked away from when it discontinued Xserve in 2011. Third, turning to NVIDIA’s NVLink to connect multiple chips would likely mark a reversal from Apple’s earlier alignment with UALink.

03 / Week Ahead: Key Events to Watch

TUE. SEP 22｜Qualcomm Snapdragon Summit

Event: Qualcomm’s Snapdragon Summit 2026 kicks off September 22–24, with new flagship smartphone chips set to take center stage.

Why It Matters: Snapdragon Summit isn’t just a smartphone event anymore. Last year brought the 2nd-gen Snapdragon X Elite for PCs and a 3rd-gen Oryon CPU, plus Qualcomm’s push into AI data centers and the custom ASIC market. The question for 2026: does Qualcomm double down on that expansion, or is another surprise in store?

Key Watch Points: Snapdragon 8 Elite Gen 6/ Gen 6 Pro, AI Accelerator Updates:

With MediaTek already shipping its first 2nm chip (Dimensity 9600), attention turns to Qualcomm’s next move — its Gen 6 is also expected to be built on TSMC’s 2nm process. The company has teased a new Hexagon NPU for the Gen 6 — up to 50% faster INT4 prefill, and tuned for Mixture-of-Experts (MoE) models that activate only a fraction of their parameters per token. Watch for how these AI gains translate into real-world benchmarks, and how pricing holds up as both 2nm costs and the ongoing memory price surge squeeze margins.

TUE. SEP 22｜Global Memory Innovation Forum 2026

Event: GMIF 2026, a major memory event, kicks off September 22 to 23 in Shenzhen, China

Why It Matters: As AI shifts from training to inference, memory itself is becoming the bottleneck. This year’s theme of GMIF, “The Future Built on AI Memory and Storage,” zeroes in on that shift: how memory and storage must evolve to keep pace with inference-heavy workloads, from enterprise-grade storage and cloud-edge-device collaboration to the emerging Token economy.

Key Watch Points: Updates from Memory Giants (e.g. Samsung on CXL, GDDR7)

Samsung headlines with updates on GDDR7 mass production, CXL memory expansion, and high-performance NAND, joined by fellow memory/storage players SanDisk, Solidigm, and Silicon Motion. Notably, Lenovo — a downstream device maker — also takes the keynote stage. Given the venue, this is also a chance to gauge how far China’s domestic memory technology has progressed.

THU. SEP 24｜Trump-Xi Summit

Event: U.S. President Donald Trump Expected to Meet Chinese President Xi Jinping in Washington

Why It Matters: This marks Trump and Xi’s second meeting this year, following their May summit in Beijing, and is expected to center on extending the US-China trade truce — including tariff relief on American energy and agricultural exports — with the broader race for AI supremacy also expected to shadow the talks.

Key Watch Points: Tariff adjustments, export controls on rare earths, AI chips

China’s dominance as the world’s top rare-earth producer gives Beijing real leverage over tariff concessions on the table. On the AI front, whether Washington eases chip export restrictions to China remains the central question — one that carries extra weight with NVIDIA CEO Jensen Huang reportedly attending Trump’s state dinner for Xi.

There’s a real use case for 4hi HBM at the edge, especially in autonomous driving and robotics. What’s less clear is whether it goes any further than that. Suppliers have made no commitment to mass-produce the spec, the base die math works against a shorter stack rather than for it, and the resulting price per Gb weakens the case for adoption in some applications.

Where 4hi Actually Makes Sense: Edge AI

Edge AI players, not data center players, are the ones showing real interest in 4hi HBM. TrendForce observes that in certain autonomous driving and robotics applications, DRAM bandwidth has gradually become a performance bottleneck for computing platforms, prompting HBM to be included in architecture evaluations.

There’s precedent for this. SK hynix supplied HBM2E to Waymo’s autonomous driving platform in 2024 and obtained automotive qualification, indicating that robotics and automotive applications have already become one of the extension areas for HBM usage.

That said, these applications are still early. Relevant specifications remain under evaluation. As a result, actual demand volumes are limited, and the short-term contribution of these segments to overall HBM demand is expected to remain very low.

Why 16GB Is a Hard Sell for the Data Center

Industry discussion around 4hi HBM is really a discussion about HBM5. Based on an HBM5 mono-die density of 32Gb, a single HBM5 4hi cube will offer a capacity of just 16GB. However, its I/O speed and bandwidth will be further enhanced compared to HBM4e.

That capacity-for-bandwidth trade-off is exactly what’s driving the split in interest. TrendForce assesses that HBM5 4hi samples are primarily being positioned as a memory architecture candidate for certain clients’ Edge AI applications. However, the likelihood of this specification being adopted in mainstream data center computing platforms is relatively low due to the following bottlenecks:

Read more

TrendForce Substack covers semiconductors and AI infrastructure in depth. Depth takes time to read, and it does not always answer the question that surfaces first on a Monday morning: what changed last week, and what should I be watching now.

AI Infra & Semiconductor Weekly Radar is built for that question, for people who follow this industry as part of their job. Every Monday, three fixed parts:

• Supply Chain Radar. Six components tracked continuously (GPU, DRAM, NAND, HDD, ABF, MLCC), each with a supply status, its current lead time against the balanced level, and one line of interpretation.

• Last Week in Tech. Developments that move the wider AI infrastructure and semiconductor supply chain, with what happened and why it matters.

• Week Ahead. The week’s key events, and what to watch to stay ahead of market shifts.

Weekly Radar is free, and included with every subscription.

Now for the first issue.

This Week in 30 Seconds

• GPU is the only one of the six components sitting at a balanced lead time. ABF substrate runs at 48 to 56 weeks against a balanced 12, the widest gap on this week’s table.

• Anthropic, OpenAI and xAI all called for slowing frontier model development last week. The supply chain question is whether hyperscalers answer by trimming capex.

• The Fed meets this week, and a hike would be its first since July 2023. Watch what that does to hyperscalers’ cost of debt.

01 / Supply Chain Radar: Where the Six Sit This Week

We track GPU, DRAM, NAND, HDD, ABF, and MLCC each week. Start with the status color, then compare the current lead time with the balanced-market benchmark and read the quick take.

02 / Last Week in Tech: Top 3 Industry Shifts

AI MODEL

Top AI Rivals Align: Anthropic, OpenAI, xAI Call for Slower Model Development

What Happened: A rare consensus is emerging among AI’s fiercest rivals. After Anthropic CEO Dario Amodei called for deliberately slowing frontier AI advances in his essay, We Must Pace the Frontier, OpenAI CEO Sam Altman and xAI founder Elon Musk echoed his concerns that capabilities are advancing faster than researchers can understand and control them.

Why It Matters: The concerns ripple across the AI supply chain — OpenAI’s possible IPO delay may be the least of it. The bigger question is whether hyperscalers pull back capex, putting chip and memory demand at risk. Yet President Trump has waved off the warnings, insisting the U.S. is “leading China on AI... and, frankly, I want to keep it that way, because whoever wins AI, wins.” Whether this push to slow down ultimately shapes the U.S.-China AI race is worth watching.

SEMICONDUCTOR EQUIPMENT / FOUNDRY

ASML Rallies TSMC, Intel and Samsung Behind 12-inch Photomasks for High-NA EUV

What Happened: ASML says moving High-NA EUV from 6-inch to 12-inch photomasks could boost productivity 40%, making the costly systems more cost-effective. The partners target a 12-inch mask pilot line by 2031 and advanced-node production by 2033, per TSMC—while Samsung eyes DRAM adoption as early as 2028.

Why It Matters: This marks TSMC’s first concrete High-NA EUV timeline—2030, aligning with its A12-and-beyond roadmap—after years of conservative signaling on the technology. For ASML and the broader upstream lithography and materials supply chain, the commitment offers reassurance of demand and could catalyze a new investment cycle.

CONSUMER / MEMORY

Apple’s New iPhone Launch: Foldable Duo Debuts, iPhone 18 Pro Up $100 on Memory Costs

What Happened: Apple unveiled its first foldable iPhone, Duo, alongside the iPhone 18 Pro and Pro Max, all powered by the A20 Pro. Memory costs pushed Pro/Pro Max prices up $100 to $1,199/$1,299; Duo starts at $1,999 with up to 2TB storage but only 12GB RAM.

Why It Matters: Apple is entering an increasingly crowded foldable market just as tightening LPDDR supply adds pressure on costs and pricing. However, despite Xiaomi and Huawei launching rivals the same week, TrendForce expects iPhone Duo shipments to hit about 5 million units in 2026, giving Apple a 24.8% market share and making it the No. 2 foldable brand behind Samsung.

03 / Week Ahead: Key Events to Watch

MON. SEP 14｜Gulf-Iran Diplomatic Meeting on Strait of Hormuz

Event: Gulf-Iran Diplomatic Meeting on Strait of Hormuz

Why It Matters: Gulf foreign ministers from the six-member Gulf Cooperation Council are set to meet Iran’s top diplomat for the first time since the February war, eyeing to secure a deal temporarily managing shipping through the Strait of Hormuz.

Key Watch Points: Whether a formal agreement would be reached to ease the oil-price pressure that’s been raising energy costs, as well as the supply squeeze on critical gases and upstream chip materials that’s been building since the strait’s closure in March.

THU. SEP 15｜Federal Open Market Committee (FOMC) Meeting

Event: FOMC Sept. Meeting: Rate Decision Ahead

Why It Matters: A hike would reportedly be the Fed’s first since July 2023, ending a 3-year pause. Middle East conflict has pushed oil near $100 and kept inflation elevated, reinforcing Chair Warsh’s hawkish tilt into the September meeting.

Key Watch Points: Whether the Fed holds steady or hikes through year-end; how that decision feeds into hyperscalers’ cost of debt and near-term capex discipline; and how sustained inflation pressure weighs on end-consumer demand for tech and cloud services in coming quarters.

FRI. SEP 17｜Huawei Connect 2026

Event: Huawei Connect 2026

Why It Matters: Huawei Connect 2026 is expected to showcase how Huawei plans to scale industrial AI adoption, expand its open-source ecosystem, and roll out next-generation AI infrastructure and developer tools amid tightening global hardware constraints.

Key Watch Points: Huawei’s Next-gen AI Chip Roadmap: Following its rollout of the Ascend 950PR and 950DT last year, all eyes are on whether Huawei will push its AI accelerator timeline even further. Other key technical updates to monitor include progress on LogicFolding architecture, as well as proprietary memory advancements like HiBL and HiZQ.

From OCP APAC and Hot Chips in August through SEMICON Taiwan in September, advanced packaging has continued to gain momentum across the semiconductor industry. Why does advanced packaging matter? Transistor scaling is approaching its physical limits, so to maximize efficiency within a single package, the industry is moving rapidly toward chiplet stacking and heterogeneous integration.

In our previous article, we looked at the advanced packaging market as a whole. We also compared TSMC’s CoWoS and Intel’s EMIB, the two leading 2.5D platforms, on specifications and key customers. This article turns to 3D packaging, and to hybrid bonding in particular.

Types of advanced packaging: 2.5D, 3D, and 3.5D

Quick recap: 2.5D packaging uses an interposer with extremely high routing density, enabling faster signal transmission and lower power consumption between dies. Examples include TSMC’s CoWoS and Intel’s EMIB (which embeds a small silicon bridge in the substrate instead of using a full interposer).

3D packaging stacks dies vertically to shorten the communication distance between them, as in TSMC’s SoIC and Intel’s Foveros Direct 3D. Both enable an integrated “3.5D” solution that combines 2.5D and 3D packaging in a single architecture. Multiple chips are vertically stacked into a single composite IC, which is then integrated with HBM or other peripheral ICs through 2.5D packaging.

According to TSMC, SoIC with 3D interconnect offers 56x interconnect density and 5x power efficiency over CoWoS with 2.5D interconnect. TSMC commenced mass production of SoIC with a 6µm bond pitch in 2025, and the company expects to further scale SoIC to a 4.5µm pitch by 2029.

On the Intel side, Foveros Direct reached volume production in 1H26 with the Clearwater Forest Xeon 6+ at a 9µm bond pitch. A second generation targeting 3µm is on the roadmap.

Related report: 2Q26 Revenue Ranking among Top 10 Global Foundries

Not only does 3D IC enable logic-on-logic stacking, but it also opens up possibilities for memory-on-logic or logic-on-memory stacking. For example, 3D DRAM architecture places DRAM directly on top of the logic die.

Building upon the foundation of 3D ICs, the industry is also striving to miniaturize optical components, integrate them into silicon chips, and co-package them with EICs to form optical engines, a technology known as CPO. This paradigm further elevates the complexity of 3D packaging. One example is TSMC’s COUPE, which utilizes hybrid bonding to integrate EICs and PICs. COUPE has been applied in NVIDIA’s Spectrum-X Photonics and Tomahawk 6-Davisson.

ASE has introduced its SiPh Optical Engine, which uses micro-bump technology to vertically bond the EIC and PIC. Intel has launched the OCI (Optical Compute Interconnect) chip that integrates the laser into the PIC, while GlobalFoundries has unveiled the SCALE (Silicon Photonics Co-packaged Advanced Light Engine) platform, which combines FAU and Fiber Array.

Behind the paywall, we explore:

• Micro-bump + TCB vs. hybrid bonding, and where each is adopted

• Alignment accuracy across major hybrid bonder suppliers, and who is closing the gap

• Three challenges beyond bonding, and how the industry is responding

• Two indicators to track: TSMC’s SoIC capacity plan and Besi’s order intake

Related report: 2026 3D IC Outlook: SoIC Ramp-Up, Rise of STCO

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Over the past year, capital expenditures at the five major US CSPs—Amazon, Microsoft, Google, Meta, and Oracle—have doubled, and that growth curve is clearly visible. But CapEx alone may only tell half the story. Financial disclosures reveal another notable trend: signed, not-yet-commenced lease commitments, which have collectively reached approximately US$1.16 trillion across the five. While these payments are not current-period CapEx, they are contractually committed. Amazon’s disclosures cover group-wide mixed uses (e.g., fulfillment centers), while the other four CSPs each specify in their notes that the commitments are data center-related.

It is evident that self-build construction pipelines can no longer keep pace with the explosive demand for compute capacity. The CSPs are accelerating their reliance on external developers to secure future capacity, marking a strategic shift toward a dual-engine expansion model driven by both self-builds and leasing. In this article, TrendForce analyzes the overall capacity trends, self-build versus leasing strategies of these five CSPs, and what this US$1.16 trillion figure signals for the future of data center expansion.

Related report: NVIDIA Data Center Boom Fuels GB/VR Rack Demand

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OpenAI and Anthropic have led AI model development since AI applications first took off in 2022 and 2023. From the second half of 2023, however, Alibaba and DeepSeek began catching up with open-source models, and DeepSeek R1 sent shockwaves through the market when it launched in January 2025. Then, following the release of Moonshot AI’s Kimi K3 in July 2026, the gap between leading Chinese and US models has narrowed significantly, prompting market discussion of a “second DeepSeek moment” and of the broader US-China AI contest.

This article goes beyond Kimi K3 itself. It compares China’s mainstream open-source models on both market and technical dimensions, and assesses the competitive position of Chinese models against their US counterparts.

Kimi K3: The Largest Open-Source Model to Date

On July 16, 2026, Moonshot AI, the Chinese AI startup backed by Alibaba and Tencent, opened the API access for its flagship model Kimi K3, and formally released the full weights on July 27.

Kimi K3 is a 2.8T-parameter MoE model, and activates about 104.2B parameters per token. It contains 896 experts, with 16 activated per token for a sparsity of roughly 56, alongside 2 shared experts. This makes Kimi K3 the largest open-source model in the world at present.

DeepSeek followed on July 31 with the official launch of DeepSeek V4 Flash, an extremely lightweight model at just 284B total parameters and only 13B active MoE parameters. The higher-tier DeepSeek V4 Pro, at 1.6T total parameters, released on August 13.

Alibaba Cloud released the weights for its flagship model Qwen 3.8 Max on August 14. It carries 2.4T total parameters with 95B active MoE parameters, making it the world’s second largest open-source model behind Kimi K3.

We will then compare Kimi K3, Qwen 3.8 Max, and DeepSeek V4 Flash on specifications, performance (based on the benchmarks from Artificial Analysis), and API pricing, and analyze the market positioning of each.

Related report: Kimi K3 Dominates Global Open-Source Models: Core Technologies and the New US-China AI Race

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Advanced packaging has become one of the most closely watched battlegrounds in the AI chip supply chain. Back in May, we took a close look at some of the key bottlenecks, including SeWaRe micro-cracking in glass substrates and warpage in panel-level packaging. The industry is moving fast. TSMC continues to expand CoWoS capacity aggressively, while reportedly developing an “EMIB-like” approach of its own. Meanwhile, Intel’s EMIB-T has reportedly seen a significant yield improvement, intensifying the rivalry between the two advanced packaging heavyweights.

Against this backdrop, TrendForce maps out the latest developments in 2.5D and 3D advanced packaging, from the architectural differences between EMIB and CoWoS, to capacity trends, customer distribution, and what comes next as the industry moves toward panel-level packaging, glass substrates, and 3D stacking.

Chiplet Architecture: It All Comes Down to Interconnects

To understand why advanced packaging has become so critical, it helps to start with how chip design has been evolving.

As semiconductor nodes continue to shrink, transistor architecture has evolved in parallel. For instance, when semiconductor technology moved from 28nm to 16nm, the industry shifted from planar transistors to the FinFET (Fin Field-Effect Transistor) architecture. The next major transition begins at 2nm, marking the start of the GAAFET (Gate-All-Around FET) era.

Although the CFET (Complementary FET) architecture has already been developed for sub-1nm nodes, the cost of process scaling continues to climb. In response, IC designers have begun adopting a disaggregation strategy, breaking a single chip down into multiple chiplets. This means components that do not require extreme scaling are separated out, and only the core portions of the chip are shrunk further.

Realizing the full potential of a chiplet design depends on the interconnect quality between dies, which is precisely where advanced packaging comes in. By packing chiplets tightly together, advanced packaging enables high-bandwidth, low-latency interconnects.

Related report: The 2026 Semiconductor Inflection Point: Scaling from 2nm GAA to the Era of ASIC Sovereignty

2.5D Packaging: EMIB vs. CoWoS

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s 2.5D advanced packaging technology. It integrates two sequential processes: CoW (Chip-on-Wafer), in which multiple dies are bonded onto a silicon interposer via micro-bumps, and oS (on-Substrate), in which the interposer is subsequently bonded onto the package substrate.

At 2026 OCP APAC Summit, TSMC stated that its 5.5x reticle size CoWoS is now in volume production, with yields consistently topping 98% across multiple AI customer products and reaching as high as 99% in some cases. The company expects to scale beyond 14x reticle size by 2029.

The key difference between Intel’s EMIB and CoWoS lies in the interposer. EMIB embeds a silicon bridge directly into the substrate to serve as the communication link between chips, eliminating the need for a full-size interposer and reducing cost as a result.

Assuming comparable yield stability between the two, Intel’s EMIB architecture offers lower cost potential than TSMC’s CoWoS by design. As for reticle size, Intel previously noted that its EMIB-T will scale to more than 8x this year and beyond 12x by 2028.

Although performance and reliability at scale have yet to be fully validated, the technology has already attracted interest from major ASIC vendors. At its 2026 Q2 earnings call, Intel CEO Lip-Bu Tan said the company is now focused on ramping EMIB-T into high-volume production to support customer ramps in 2027.

Taiwan’s OSAT providers have also been moving quickly in 2.5D packaging. ASE’s Fan-Out Chip on Substrate (FOCoS) uses multiple RDLs to integrate processors, memory, and I/O chips, with RDL layer counts scaling from 3 or 6 layers up to as many as 12. According to the company, this delivers interconnect density roughly 50x that of traditional flip-chip packaging, and over 200x with FOCoS-Bridge. SPIL, meanwhile, has developed FOEB (Fan-Out Embedded Bridge), which embeds silicon bridges within the RDL layer to enable near-monolithic, high-density, short-reach connections between dies.

Related report: Foundry Market Bulletin - Aug. 17, 2026

Behind the paywall, we explore:

• EMIB vs. CoWoS full spec comparison and key customers

• CoWoS capacity share among major customers

• Updates on glass-based solutions and 3D/3.5D packaging

• TrendForce view on overall supply and price trends

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This year, the Chinese government has actively encouraged the adoption of domestic AI chips. This policy push will likely provide priority support to high-potential domestic players, allowing them to substantially expand their market share in China’s high-end AI server market. At the same time, the domestic ecosystem is maturing in key areas such as advanced foundry nodes, advanced packaging, and thermal management. Together, these developments are moving China’s AI infrastructure away from its heavy reliance on foreign GPUs, toward a dual-track model of “domestic GPUs + proprietary ASICs.”

This article will explore:

• How China’s high-end AI chip supply structure is being reshaped

• WAIC 2026: The shift toward rack-scale supernode architectures

• TrendForce View on component demand driven by supernode architectures

Related report: Global Capex Rises as China Builds AI Autonomy

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In June 2026, the US Department of Defense added Unitree to its Section 1260H list of “Chinese Military Companies”. On July 28, the US Federal Communications Commission (FCC) announced plans to restrict imports of new foreign-made humanoid and quadruped robots. The move is driven not only by national security concerns but also by an effort to boost the development of America’s own advanced robotics industry. Widely interpreted as targeting China, it begs an obvious question: just how critical a role does China actually play in the global supply chain?

Related report: US Restrictions on Humanoid Robot Imports Temporarily Curb Chinese Competition While Driving Long-Term Supply Chain Restructuring

Policy Initiatives and the Industry Ecosystem for Humanoid Robots in China

China’s humanoid robot industry entered a phase of rapid growth in 2025, with companies such as Unitree and AgiBot each shipping over a thousand units that year. According to TrendForce, China’s 2026 production volume is expected to account for nearly 70% of the global total. Driven by government policy, the industry is moving toward standardization and use-case segmentation, facilitating subsequent model training and data collection while providing a cohesive framework for industry development.

At the same time, China is deploying state-backed capital to subsidize the development of the robotics sector, while promoting open-source frameworks to incentivize the sharing of technologies and research outcomes, reducing redundant R&D expenditures. Technologically, these policies explicitly target three foundational pillars: embodied AI models, motion control algorithms, and core hardware components, systematically cultivating a comprehensive industry ecosystem.

In terms of product development, China currently concentrates on general-purpose functionality, which requires robots to operate across multiple scenarios and tasks. This calls for hardware specifications with mature motion control, environmental sensing, and recognition capabilities, combined with large AI models and highly efficient, low-latency computing, to approach human-like reaction speeds and intelligent behavior.

However, at the current stage, limited production capacity and high unit costs make it difficult to deploy humanoid robots at scale for data collection in the near term. Compared to household environments, which involve high use-case diversity and extreme privacy sensitivity, structured settings such as logistics warehouses and factory floors offer greater environmental controllability and easier data access, making them the primary deployment scenarios at this stage.

Below, we will explore:

• Why the shift from extreme performance to practical reliability is changing what key components need to deliver

• How China is targeting the movement and power planes as its breakthrough point for domestic substitution, with a supply chain breakdown

• TrendForce’s view on what it will really take for China to scale up

Related report: Development of China’s Humanoid Robot Industry: Supply Chain Self-Sufficiency and Challenges for Key Components

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For instance, researchers have rethought how many Key-Value vectors a model actually needs to keep around. Alongside that, a separate line of work has asked whether those vectors need to be stored at full precision at all. But even when KV Cache’s capacity requirements are lower, it can still be slow to read. Some companies are tackling this bandwidth problem directly, rethinking how models generate tokens in the first place.

Behind the paywall, we break down:

• How Google and DeepSeek reworked attention mechanisms via GQA and MLA

• How NVIDIA’s KVTC and Google’s TurboQuant quantize KV Cache down to a fraction of its size

• How Google, Meta, and DeepSeek are racing to fix the decode bandwidth bottleneck, from MTP to DiffusionGemma

• TrendForce View: what solving the KV Cache bottleneck means for memory demand

Related report: Overcoming the Memory Bottleneck: CXL Expansion and KV Cache Compression Innovations

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Chipmakers, CSPs, and infrastructure vendors are now converging on the problem from opposite ends. Part 1 of this series looks at capacity expansion: how CXL technology and KV Cache offloading are creating a new tier in the memory hierarchy, and which companies are positioned along the way. Part 2 looks at footprint compression, where attention mechanism improvements and KV Cache quantization shrink how much room the KV Cache needs in the first place.

Why KV Cache becomes the bottleneck

If you read our previous article on AI memory, you will recall that the KV Cache is a dedicated memory space used during inference to store the KV (Key-Value) vectors generated in the prefill phase. By reading from the KV Cache instead of recalculating those vectors at every decode step, AI models dramatically improve inference efficiency.

The catch is that the KV Cache is dynamically allocated. Its memory footprint scales with both the context window and the batch size:

Total Size of KV Cache (Bytes) = 2 × layers × KV heads × head dimension × sequence length × batch × precision (Bytes)

Consider Llama 3 70B loaded in FP16 without GQA (using standard MHA). The model weights occupy roughly 140GiB, so early on, most of the available memory capacity is used to store the weights. But as the context window scales (assuming batch size of 1), the KV Cache consumes 160GiB at 64K, already exceeding the memory capacity required for the model weights. At 128K, it swells to 320GiB, roughly 2.3 times the size of the model weights. KV Cache becomes the primary driver of memory exhaustion.

Behind the paywall, we dig into capacity expansion solutions designed to resolve the KV Cache bottleneck:

• The mechanics behind CXL

• Enfabrica’s EMFASYS

• Penguin Solutions’ MemoryAI KV Cache Server

• Marvell’s Structera S

• Meta’s Vistara and MemServer

Related report: Overcoming the Memory Bottleneck: CXL Expansion and KV Cache Compression Innovations

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This piece is written for readers looking to build a clear, foundational understanding of AI memory requirements.

Contents:

1. Memory requirements for AI training

2. Memory requirements for AI inference

3. How the memory structure changes as the industry moves from training to inference

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Memory Requirements for AI Training

AI training refers to the process of using a training dataset to teach an AI model new capabilities. AI inference refers to the process of applying an already-trained model to new data to generate a response. Because these two stages require very different types of memory, memory architecture has diversified rapidly in recent years.

Taking today’s dominant Transformer architecture as an example, the training process consists of three main stages:

1. Forward Pass: The weights of each layer are read from memory into the compute die, where large-scale matrix multiplication produces a predicted output. A loss function then compares this output against the correct answer to measure the error (loss).

2. Backward Pass: Following the chain rule, the model reads the activations temporarily stored during the forward pass, layer by layer, and computes gradients that match the size of the weights.

3. Optimizer Update: After reading the gradients, the model updates and writes back the weights themselves, along with two optimizer state tensors of the same size as the weights (first-moment m and second-moment v).

Because the model must repeat these three stages over and over to minimize loss and converge, memory access speed becomes the key factor determining training efficiency.

This is the context in which HBM (High Bandwidth Memory) emerged: multiple layers of DRAM stacked vertically and connected via TSV. Unlike conventional DRAM, which connects over relatively slow PCIe (PCIe 6.0 x16 offers 128 GB/s of unidirectional bandwidth), HBM is packaged side by side with the compute die on the same interposer, shortening the data path. A single HBM stack can deliver more than 2 TB/s of bandwidth (HBM4 offers over 1 GB/s per pin in one direction across 2,048 pins), which has significantly accelerated the industrialization of AI.

The memory hierarchy gained a new tier, HBM, during the training era, filling the gap between on-chip SRAM and conventional DRAM.

Related report: 3Q26 HBM Datasheet

Memory Requirements for AI Inference

AI inference consists mainly of two stages:

1. Prefill: The input prompt is processed in parallel in a single pass. The Key and Value vectors for each layer are computed and stored in memory (the KV Cache), and the first output token is generated at the same time.

2. Decode: Key and Value vectors are read from the KV Cache to generate tokens one at a time, while newly computed Key and Value vectors are continuously written back into it, until the response is complete.

Because the Decode stage requires repeated token-by-token reads and writes to the KV Cache, and because KV Cache size keeps growing with the number of conversation turns, context window length, and batch size, relying on HBM alone is increasingly insufficient to keep up with growing inference demand. Memory capacity has become a second critical bottleneck, alongside bandwidth.

Unlike the relatively mature memory architecture built for AI training, AI inference memory architecture is only now developing rapidly alongside test-time scaling. Vendors are still actively experimenting with different memory approaches, and the memory hierarchy is in the middle of a paradigm shift.

To address the growing capacity needs of KV Cache, memory makers SanDisk and SK hynix announced a partnership in August 2025 to develop HBF (High Bandwidth Flash), which stacks multiple layers of NAND vertically and connects them via TSV. At an expected bandwidth of 1.6 TB/s, a single HBF stack is projected to offer around 512 GB of capacity, roughly ten times or more that of HBM (a 16-Hi HBM4 stack offers 48 GB), filling the gap between HBM and conventional DRAM.

While HBF has yet to reach mass production, many vendors are concurrently using KV Cache offloading to move less frequently used KV Cache down to lower tiers of memory, easing the burden of storing large volumes of KV Cache. In this context, NVIDIA introduced the concept of SSD POD in 2026, filling the gap between local SSD and shared storage.

Notably, beyond HBF and SSD POD, some inference ASIC startups have introduced high-speed SRAM to break past HBM’s speed limits. Groq (whose inference technology license and core team were secured by NVIDIA in December 2025) and Cerebras, for example, use large areas of on-chip SRAM to significantly increase decode speed.

Related report: 2026 Trends: Memory for New AI Inference Demand

Memory Structure Changes from Training to Inference

In the first half of 2026, as inference demand continued to surge, NVIDIA announced it will incorporate the Groq LPX chip into its Rubin series, expected to be available later this year, alongside the introduction of CMX (Context Memory Storage Platform) and the Vera CPU Rack.

Google also unveiled the TPU v8i, designed specifically for inference, which carries 72 GB more HBM3e and 384 MB more SRAM than the TPU v8t, which is designed for training.

Beyond these two major players, a number of AI ASIC startups building inference-specific chips have been active in the first half of 2026: SambaNova launched its fifth-generation chip, the SN50, in February 2026; Cerebras filed for an IPO in April 2026 and announced partnerships with OpenAI and AWS; and Etched announced in June 2026 that its Sohu chip had successfully taped out at TSMC.

Looking at how the training era was dominated almost entirely by HBM, compared with the far more varied inference landscape today, the design choices for the memory hierarchy can be expected to keep diversifying going forward.

Coming up next

In our next piece, we take a closer look at how industry leaders are turning to CXL expansion and KV Cache compression to address the memory bottleneck, along with what this means for the memory market going forward. Subscribe so you don’t miss it.

Contents:

1. China’s ultra-bionic robot boom, and the companion economy behind it

2. Why the US is betting on AI while China bets on scale

3. Who really controls the supply chain, mapped out with our new CSCII index

China’s Ultra-Bionic Robots Open a New Companion Economy

As generative AI matures and social trends such as aging populations, falling birth rates, and rising numbers of single-person households reshape demand, robots are shifting from labor substitutes to emotional companions, driving rapid development in China’s ultra-bionic humanoid robots. Unlike traditional humanoid robots that emphasize bipedal walking, lifting, and task execution, these products prioritize lifelike appearance, emotional expression, and natural interaction, aiming to build long-term human-robot relationships. China’s market currently features diverse technical approaches. For instance, AheadForm’s Origin F1 focuses on eye contact, micro-expressions, and a desktop half-body design, using a high degree of facial articulation to reduce the uncanny valley effect. Noetix Robotics’ Hobbs 3 Series targets the desktop companion market, emphasizing synchronized voice and expression, emotional interaction, and family companionship.

Related report: Humanoid Robot Quarterly Report - 3Q26

Unlike most ultra-bionic robots, which use half-body or fixed designs, UBTECH’s UWORLD U1, launched in June 2026, is a full-size humanoid. It combines highly realistic silicone skin, 88 degrees of freedom, a biomimetic cervical spine, and full-body motion control, enabling not only natural facial expressions but also more realistic interaction through complete body movement. On the AI side, it incorporates an emotion-aware LLM that integrates long-term memory, multimodal perception, voice interaction, and on-device AI inference, allowing it to adjust dialogue and interaction style based on the user’s emotional state. TrendForce observes that China’s ultra-bionic humanoid robots are gradually expanding into companionship, entertainment, elder care, and digital content applications, with competition shifting from hardware performance to emotion AI, content services, and overall user experience.

For the supply chain, beyond existing humanoid robot components such as servo motors, reducers, and dexterous hands, demand is also expected to grow for high-fidelity silicone materials, electronic skin, multimodal sensors, microphone arrays, vision modules, edge AI chips, and emotion models, giving rise to a new industry ecosystem that combines mechanical, AI, and consumer electronics characteristics.

US-China Divergence: Intelligence vs. Scale

• US: Deepening the AI Ecosystem, Shifting Value from Hardware Specs to Intelligence

The AI ecosystem remains the US’s greatest advantage in humanoid robotics. As generative AI, Vision-Language-Action (VLA) models, and world models mature rapidly, the value of humanoid robots is shifting from hardware specifications to intelligence. Major players such as NVIDIA continue to advance Physical AI platforms including Cosmos, Isaac Lab, and GR00T; Google DeepMind has launched Gemini Robotics to strengthen robotic understanding; and OpenAI is participating in embodied AI model development through investment and research. Together, US firms are forming a complete technology ecosystem spanning large language models, robotics platforms, simulation environments, and AI chips. This reflects the view that as humanoid robots move into complex environments, competitiveness will depend on environmental understanding, multi-step task planning, cross-scenario generalization, and continuous learning.

US companies’ strategies have also shifted from demonstrating hardware capability to building AI capability. Tesla‘s Optimus Gen 3 continues real-world validation on factory floors, with future production focused on improving the robot’s generalization so the same AI can quickly adapt to different work environments. Figure AI is deepening partnerships with large enterprises to train its models on large volumes of real factory data. Boston Dynamics combines years of motion control expertise with AI to strengthen autonomous operation in complex environments. Apptronik generates high-quality data through extensive real-world deployment, feeding it back into the Gemini Robotics training pipeline.

In short, US firms are focused on building a data flywheel, aiming to continuously refine their models with large volumes of real-world data and differentiate their products through AI capability.

• China: Accelerating Supply Chain Integration, Shifting from Product Iteration to Scale Deployment

By contrast, China’s humanoid robot development more closely resembles the early development model of electric vehicles: building a complete supply chain and lowering costs quickly, then achieving economies of scale through high shipment volumes. Under this approach, core components such as servo motors, reducers, and lithium batteries can be localized quickly, lowering costs and significantly shortening development cycles.

The two most representative companies are Unitree and AgiBot: Unitree has built a reputation for high value for money and rapid product iteration across both quadruped and humanoid robots, while AgiBot scaled its production from 1,000 to 5,000 units in about a year, and then from 5,000 to 10,000 units in just three months. This shows that China’s advantage today extends beyond manufacturing cost. Its supply chain maturity allows new products to complete component validation, pilot runs, and mass production quickly, giving it a faster iteration pace than its Western competitors.

Notably, as factories, logistics operations, and public venues continue to adopt humanoid robots, China is rapidly accumulating real-world data through large-scale deployment, extending its supply chain advantage into a data advantage. This could help China’s humanoid robot industry form a positive cycle of “deploy, collect data, update the model, redeploy.“ As models continue to improve, the AI gap between China and the US may narrow as a result of China’s data scale.

Supply Chain Power: Component Cost Breakdown and the CSCII

As the humanoid robot industry rapidly takes shape, “who controls the supply of key components” has become a core question in assessing each region’s industrial competitiveness. TrendForce has designed the Component Supply Chain Influence Index (CSCII) to systematically analyze how well each region’s suppliers control different key components.

The CSCII is a composite indicator combining qualitative and quantitative assessment; it is not a single, directly verifiable statistic. Ratings are weighted across five dimensions using expert judgment:

1. Industry scale position: measuring a component’s global revenue share across industries, reflecting manufacturing scalability.

2. Technology barriers and substitutability: measuring patent concentration and how quickly followers can catch up.

3. Humanoid robot application penetration: measuring the breadth of actual design-in by mainstream OEMs in humanoid use cases.

4. Production capacity and expansion momentum: measuring supply flexibility and manufacturing scaling speed.

5. Policy and geopolitical supply resilience: factoring in export control exposures and domestic policy support.

Let’s break it down by region:

• China has the most comprehensive presence across all four planes, leading the Power Plane and rated “Strong” in both the Mental and Movement Planes, with its strength built on manufacturing scale and broad component coverage.

• The US holds the most pronounced leadership in the Mental Plane, where NVIDIA and Qualcomm command a near-monopoly in AI chips and computing platforms.

• Europe is rated “Strong” in both the Sensing and Movement Planes, with its strength concentrated in precision manufacturing. Its companies are less well known than major players in other regions, but carry deep technical value, with German suppliers holding a distinct edge in encoders.

• Japan holds a solid lead in the Movement Plane, and its strength is highly concentrated in mechanical transmission, where companies have established deep technology barriers.

• South Korea is currently rated “Strong” in the Power Plane, supported by active battery investments from LG and Samsung. Other planes will depend on stronger public-private collaboration to accelerate ecosystem development.

TrendForce View

As the humanoid robot industry moves toward commercialization, companies are shifting their focus from the novelty of product iteration to the durability of their business models. The US and China are pursuing two distinctly different competitive strategies: the US is emphasizing AI, large models, and high-value applications to make its products smarter, while China is leveraging its full manufacturing ecosystem and supply chain advantages to accelerate product iteration and scale deployment.

China’s rapid rise is putting real pressure on US manufacturers today. But over the long run, what will determine the global humanoid robot industry’s landscape is whether companies can build business models that combine scale deployment, data accumulation, and sustainable profitability for their target markets. Given the diversity of commercial use cases and user needs, TrendForce believes that the future market is unlikely to be winner-take-all — multiple players are likely to coexist.

China’s path in the robotics industry is a complex story on its own. In Part 2, we’ll look at how Chinese manufacturers are borrowing from the electric vehicle playbook to localize key components. Subscribe so you don’t miss it.

From a CapEx perspective, North American cloud service providers (CSPs) have significantly raised their 2026 capital expenditure guidance, with investment increasingly concentrated in the deployment of high-performance GPU clusters, in-house ASIC development, and next-generation data centers designed to support high-power-density computing.

In China, leading CSPs such as ByteDance and Alibaba are making equally substantial commitments to compute infrastructure. The continued rollout of the East Data West Computing (EDWC) initiative (which redirects eastern computing workloads to western regions to optimize data center distribution and promote balanced regional development) has positioned AIDCs as a core link between the digital economy and the modern power grid.

However, the three defining characteristics of AIDCs — high power density, extreme load volatility, and massive energy consumption — place immense pressure on power systems. To ensure the stable operation of compute workloads, energy storage systems have evolved from an “optional add-on” to “mission-critical infrastructure.”

The following analysis covers energy storage demand dynamics across North American and Chinese markets, as well as the energy storage solutions offered by major Chinese manufacturers. Insights on the Chinese market draw on TrendForce’s ongoing primary research and long-term coverage of the local industry.

North America and China: Different Challenges, One Common Need

The enormous power demands of AIDCs are driving regional grid loads sharply higher, widening energy supply gaps. North America and China face distinct challenges, but both are accelerating energy storage deployment as a result.

• North American Market: Grid Constraints and Gas Turbine Shortages Drive Urgent Storage Demand

North America is a core hub for global AIDC development, with electricity supply heavily dependent on natural gas — gas-fired generation accounts for 40–50% of the energy mix across most regions. Surging AIDC power demand has further tightened large gas turbine supplies. Faced with growing supply-demand imbalances and an escalating risk of grid outages, AIDC operators are under pressure to increase their share of renewable energy generation. However, the inherent intermittency and volatility of solar and wind power mean that robust energy storage systems are essential to guarantee 24/7 uninterrupted data center operations.

• Chinese Market: Policy Support and Resource Optimization Accelerate Storage Integration

China’s AIDC build-out is driven by national strategic initiatives, with optimizing regional resource allocation at its core. The government has incorporated “Computing-Power Synergy” (the coordinated planning of AI compute infrastructure and power systems) into new infrastructure projects, encouraging compute facilities to deploy advanced and grid-forming energy storage systems.

In practice, power grids in China’s eastern compute hubs are approaching their load capacities, while grid infrastructure in renewable-rich western regions remains relatively fragile. Ultra-high-voltage (UHV) transmission networks alone cannot fully mitigate the pulsed load shocks generated by AIDCs. Coupled with regulatory requirements for green electricity consumption, grid-forming energy storage and long-duration energy storage (LDES, predominantly 4–8 hours) have consequently become standard configurations for compute hubs, further accelerating the pace of energy storage integration.

Related report: Mutual Empowerment of AI Computing Power and Electricity: Power Grid, Long-Duration Energy Storage, and New Power System Transformation

AIDC Storage Demand on Two Fronts

AIDC energy storage is primarily deployed across two domains: the data center side and the generation side. On the data center side, during Large Language Model (LLM) training, AIDCs experience severe, pulse-like power transients that place extreme demands on power continuity and grid resilience. To address this challenge, NVIDIA's 800V DC architecture white paper highlights the need for a layered storage approach, leading to a two-tier deployment: external (facility-level) and internal (rack-level) storage.

• External (Facility-Level) Storage serves as reliable backup power, keeping grid load volatility under 2%; BESS can also participate in grid peak shaving and ancillary service markets. Additionally, they provide essential frequency regulation for on-site captive generation such as gas turbines and nuclear reactors.

• Internal (Rack-Level) Storage addresses immediate power anomalies within the facility. BBUs leverage DC-DC conversion for high efficiency, low parasitic power draw, and a compact form factor, suitable for distributed integration directly inside high-power-density AI server racks. Supercapacitors complement this by enabling instantaneous discharge of massive electrical transients with near-zero energy loss.

Related report: NVIDIA AI Server Power Roadmap & Data Center Build Risk

On the generation side, as the costs of solar modules and energy storage systems continue to decline, the levelized cost of energy (LCOE) for solar-plus-storage has fallen below that of conventional generation sources such as natural gas and nuclear power, giving solar-plus-storage a distinct cost advantage. As the green electricity transition accelerates AIDC adoption of renewable energy globally, energy storage systems play a critical role in ensuring stable alignment between variable renewable supply and the continuous, high-load power demands of data centers.

China’s Energy Storage Supply Chain: Accelerating Cell and Systems Technology Upgrades

This wave of AIDC-driven demand is accelerating technology development among Chinese energy storage manufacturers.

• Cell technology is advancing toward higher reliability, efficiency, and safety.

• Systems technology encompasses grid-forming storage, high-voltage DC (HVDC) architecture, liquid cooling, and long-duration energy storage.

TrendForce View

The global energy storage market in 2026 is entering a new phase of demand restructuring driven by AIDCs. Across the value chain, solar, wind, and storage are integrated on the generation side; grid-forming storage supports the grid side; and layered BESS, BBU, and supercapacitor protection covers the load side. At the dispatch level, AI-powered energy management systems (EMS) enable real-time matching of computing load and power supply. Together, these form a new type of infrastructure defined by the efficient synergy of computing power, electric power, and energy storage.

TrendForce believes that AIDCs will continue to provide steady growth momentum for the energy storage sector. Energy storage will play an increasingly critical role in securing compute reliability and advancing energy transition.

For an in-depth analysis and vendor breakdown, access our full report: 2026 Energy Storage Turning Point: AIDC Fuels Dual-Engine Demand Growth

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